ASM waitpeq
I see in the manual that waitpeq takes 5+ cycles. What does the + sign mean? My tests using a counter in NCO mode shows exactly 5 clock cycles needed no matter what I do to the pulse width or rep rate. Does it have something to do with a state change on the waitpeq pin occurring between clock transitions? If so, would the maximum clock cycles be just short of 6?
Tom
Tom
Comments
So once the specified state is reached, no more than 5 clock cycles elapse before execution starts with the next instruction. Right?
Tom
Tom