ASM waitpeq

TomS

I see in the manual that waitpeq takes 5+ cycles. What does the + sign mean? My tests using a counter in NCO mode shows exactly 5 clock cycles needed no matter what I do to the pulse width or rep rate. Does it have something to do with a state change on the waitpeq pin occurring between clock transitions? If so, would the maximum clock cycles be just short of 6?

Tom

Mike Green

The + sign means that the waitpeq takes as many clock cycles as it takes for the selected pin(s) to reach the state specified. The minimum is 5 (4 for the instruction itself and at least 1 state to test for the specified condition.

TomS

Thanks Mike,

So once the specified state is reached, no more than 5 clock cycles elapse before execution starts with the next instruction. Right?

Tom

Mike Green

The extra 4 clock cycles are "up front". The test for the required state is in the last cycle of the instruction. If the I/O pins are already in the required state, the waitpeq takes 5 clock cycles to execute (the minimum). If the I/O pins are not in the required state, the waitpeq instruction will hang in the last cycle until the state is reached and exit on the next clock cycle.

TomS

Thanks again, That answers my question fully.

Tom

deSilva

It is a little bit more complicated, but not relevant for most applications. Have a look into "Sidetrack F" of my Tutorial for more details.