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Fast EEPROM idea — Parallax Forums

Fast EEPROM idea

acy.stappacy.stapp Posts: 10
edited 2007-09-29 06:57 in Propeller 1
Hey guys I have some ideas for a system to access 4 or 8 i2c eeproms or frams in parallel using a cog to coordinate device access and handle the protocol. I believe that since all the slaves will be behaving identically you could use one shared clock line and 4 or 8 data lines. I'm just wondering how fast a cog can run I2C and how much extra cost (not that much, I'd expect) would be incurred by running the protocol in parallel for several data lines. Anyone have experience with this?

Acy

Comments

  • Mike GreenMike Green Posts: 23,101
    edited 2007-09-29 04:29
    If you used a block of 4 pins for the SDA lines and one line for the SCL line, you could read/write 32 bits at a time rather than 8. It would be easy to duplicate the address/device-select bits across the 4 SDA lines. I've not been able to run I2C reliably at 400KHz, probably due to additional overhead due to the generalized nature of the routines I wrote. 100KHz seems to work fine. That's about 10K bytes per second.

    I suspect you'd do better with an SPI interface, like that for an SD card or one of those dataflash memories. They can often be clocked in the 10MHz or higher range.
  • Direct Digital LabsDirect Digital Labs Posts: 27
    edited 2007-09-29 06:57
    I've been able to run my own asm I2C code·at 1Mhz without any problems and plenty of headroom to implement 8-bit width. With some devices I've·been able to run them at·1.25MHz reliably so I don't see why this idea would not work.

    -Dan
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