Shop OBEX P1 Docs P2 Docs Learn Events
Increasing COG ram — Parallax Forums

Increasing COG ram

acy.stappacy.stapp Posts: 10
edited 2007-09-27 19:30 in Propeller 1
Add a cog-local memory (another 4K or 8K?) and access it similarly to hub-ram. You could alter the RDLONG/WRLONG instructions to check the C-effect bit and read or write from either Hub memory or from the cog-local memory (cog cache?). This other memory space could be used for stacks, code cache, data blocks, frame buffers, or whatever. Unlike the hub ram there would be no waiting and it would give a lot of flexibility.

Sound feasible?

Comments

  • Mike GreenMike Green Posts: 23,101
    edited 2007-09-27 03:25
    It's a nice suggestion, but it's not going to happen. Similar suggestions have been brought up before. Any additional cog memory would have to be duplicated 16 times since there will be 16 cogs on the 2nd generation Propeller and there's not room on the chip for that.
  • inserviinservi Posts: 113
    edited 2007-09-27 12:04
    Hello Mike,

    I'm very surprised by your answer ! How do you know exactly the space available in the 2nd Propeller generation ?
    If this space is already so well defined can you describe it to us ?

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    in medio virtus
  • AleAle Posts: 2,363
    edited 2007-09-27 12:41
    This was discussed already a couple times. The people from Parallax said in more words what Mike put in fewer smile.gif.
  • deSilvadeSilva Posts: 2,967
    edited 2007-09-27 12:54
    See the appropriate threads. There is no surprise in this. Compatibility is difficult to uphold and very high speed SRAM expensive. Chip design is not:" It would be nice if..." but quite predictable, given the technical constraints.
  • Mike GreenMike Green Posts: 23,101
    edited 2007-09-27 13:16
    Here's the thread: http://forums.parallax.com/showthread.php?p=617536.
  • inserviinservi Posts: 113
    edited 2007-09-27 14:11
    Thank you all.

    dro.

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    in medio virtus

    Post Edited (inservi) : 9/27/2007 2:16:01 PM GMT
  • acy.stappacy.stapp Posts: 10
    edited 2007-09-27 16:23
    Mike Green said...
    It's a nice suggestion, but it's not going to happen. Similar suggestions have been brought up before. Any additional cog memory would have to be duplicated 16 times since there will be 16 cogs on the 2nd generation Propeller and there's not room on the chip for that.

    From what I have read the prop II will have 256K of hub ram. Just steal some of that and put it for cog cache. 16@4K + 192K or 16@8K + 128K.

    I've read the whole more cogs/ram thread a few times and seen some mention of bank switching. This is just an alternative I didn't see mentioned. It would complicate the instruction decode very slightly, and would possibly be easier for a high-level compiler to generate code. It's probably already too late in the design cycle for a change like this anyway (I remember reading something about the memory block design already being done) but I just wanted to put the idea out there.
  • hippyhippy Posts: 1,981
    edited 2007-09-27 19:30
    @ acy.stapp : I brought up the issue of extra Cog Ram and using Bank Switching fairly recently ( different thread to the 150+ post blockbuster ).

    I still believe it has merit and could be quite useful, but it's not, as Mike said, going to happen for a variety of reasons. There are new abilities proposed for the Mk-II such as block read from Hub which will increase throughput, and the Large Memory Model ( or a version of it ), coupled with larger Hub size, faster execution and block reads should serve all but the most demanding Cog applications.
Sign In or Register to comment.