Using a microcontroller as a I/O controller?

MarkS

I've been designing a Motorola 68000-based microcontroller for several months now. This was supposed to be a fun and educational project for me. The only thing stopping me from completing the design is the I/O interface. Simply put, there is no good, low component, way to add addressable bi-directional I/O pins to a microprocessor. At least that's been my thinking...

...Until today...

I just had a thought that I could use a microcontroller as an addressable I/O controller. Looking at the SX48BD-G, I could use four I/O pins for the address, 16 pins to the 68000's data bus and the other 16 pins to an I/O header. I would only need a small amount of RAM on the controller(s) for a pin direction control register. Other than that, the microcontroller's software would just check the the address pins, which would act as a chip select, and if selected, transfer data between the data bus and I/O header.

Is this doable? Is there a better way?

Post Edited (MarkS) : 9/15/2007 2:23:06 PM GMT

MarkS

Something like this:

MarkS

Bump

Phil Pilgrim (PhiPi)

You'll need to make sure the SX program can respond quickly enough to conform to the 68000's bus timing requirements. I'm not familiar with the 68000, but perhaps there's some sort of wait state delay that can be employed. You used the word "bidirectional", but I don't see any R/W signal going into the SX. How will it know whether to grab data off the bus or put it on the bus?

There used to be plenty of I/O controllers available for bus-based systems. The 82C55 was a very popular chip for this and may still be available. My recommendation would be to find such a chip and use it. You'll spare yourself a lot of agony over trying to shoehorn an SX into an app for which it's ill-suited.

-Phil

David B

I've been doing something like this using an SX52 to interface to a hard drive. The SX52 D and E ports implement the 16 bidirectional data lines and the C port about 6 unidirectional control lines to the IDE hard disk, and lets clients send commands and receive results over the A and B ports. I configured the SX to communicate with its clients in nybble-wide units to cut down on the number of client IO lines needed, even though speed suffers a little.

It works great from my PC, using the parallel port for bidirectional synchronous nybble-wide communication like that old laplink protocol, to read and write hard disk sectors.

I don't know the device interface requirements of the 68000 but why not use an SX for this? I'd say why not go for it, but work through the design really carefully, because those IO pins have a way of getting used up really fast as you plan out all the necessary control bits that will be needed.

If you're interested, I'll post what I've done in the projects area.

David

MarkS

The 68000 has a clock output that is 1/10th of the processor clock and used for peripheral syncing. This would be the the clock input for the SX chip. I would need three pins from the 68000, one of the two data strobe pins(UDS or LDS), R/W, A1 and A2, and a chip select signal from the bus control logic. This would closely match the 6522 (an old parallel IO chip) interface.