C4SX: bug report

Peter Verkaik

RW Senser,

It took me a long time to find this one, as it occured while using the VP libraries
and the taskswitching at the same time.

The statement
· while (!vpUartTx_ready(tx)) ;
generated code
· 2865········································· ;· while (!vpUartTx_ready(tx)) ;
· 2866· 009E· 0019····· m043··· BANK· 16
· 2867· 009F· 05E4············· SETB· 4.FSR_7
· 2868· 00A0· 0216············· MOV·· W,tx
· 2869· 00A1· 0012············· PAGE· 1024
· 2870· 00A2· 0913············· CALL· vpUartTx_ready
· 2871· 00A3· 0703············· SB··· 3.Carry
· 2872························· ;PAGE· 0 ;missing page instruction
· 2873· 00A4· 0A9E············· JMP·· m043

As you can see, the PAGE 0 was missing. After I inserted the PAGE 0
my vpUart routine started working. This was for device SX48.

Edit: workaround for now
· while (!vpUartTx_ready(tx)) {
#pragma asmDir: PAGE 0
· }

The bug appears to be only present in page 0.
The general format to check for is:
· SB X
· JMP Y
and
· SNB X
· JMP Y

before the jump, a PAGE 0 must be inserted.
(if there was a PAGE instruction before)

Update on the VP libraries:
After correcting the missing PAGEs, my vpUartTx is running together
with a TASK for queuing outgoing data. It occupies 96 isr cycles.
Since INTPERIOD = 174, there are still 78 isr cycles left for another vp.
I will try to add a vpUartRx.

regards peter

Post Edited (Peter Verkaik) : 9/3/2007 2:10:50 PM GMT

RW Senser

Hi Peter,

Greetings.

Thanks for finding this. I'll review -- and send it to the CC1B author.

I have the next C4SX release about ready to go with the newest CC1B (version 0.7A -- there was a very small bug (having to do with commenting out "PCL") in 0.7 plus the 0.7A version inserts the 'reset <main>' that we were adding manually). I hope to have it out tomorrow or Wednesday.

Could you reply with a zip file of your latest C4SX libs? I'll get them into this next C4SX release.

Thanks,
RW Senser

RW Senser

Hi Peter,

I've not convinced myself that I have reproduced this SX48 bug.· I looked at your recent post of libraries.zip and did not see the needed code.

Could you send me a test program that shows this error?· Smaller the code, the better -- since I will send it on to bknd.· But, any reproducable case will work.

Thanks,
RWSenser

Peter Verkaik

RW Senser,

Because of the "bug" I moved all my code, except main() and iServer(), to pages 1 and beyond.
It took me some time to get the libraries to work on all call trees (interrupt, mainlevel and tasklevel)
but I succeeded.

Now that you asked to reproduce the error, I moved the mainfile routines back to page 0
(all library routines are on page 1 and beyond).
The error did not reproduce :-)
as I have still a working bidirectional uart connection.
Perhaps it was the combination of tasks and VP code after all that
made it look as if there was a page error. The fact that cc1b uses both
ret and retp makes it a bit more difficult to track.
At the moment I cannot reproduce the error so for now,
I assume there is no page problem.

I will clean up my libraries and post updates soon.

regards peter

RW Senser

Hi Peter,

Greetings. I had exactly the same thing happen with a CC1B potential bug a few weeks back: I found it, coded around it -- and later tried to reproduce it and could not. You were the one that finally nailed it with a reproducable case. <<smile>>

I'm about to release V03 of C4SX. I have what I think are your current copies in the pvlibs directory. Should I wait a day or so for you to release your latest libs 'soon'??

Thanks for the efforts,
RWSenser

Peter Verkaik

If you can wait a day, then I will have updated
libraries and a working example on how to integrate
tasks and VP's.

regards peter

RW Senser

Hi Peter,

Waiting a day is no problem.

RWSenser

Peter Verkaik

I just got them ready.

The schematic explanation of the taskswitching is in the pdf.
The vp_test.txt is the same as vp_test.c but for online viewing.
sxchips.zip contains the sx header files with my additions (eg. membank defines
and chiptype and chipsize defines)
libraries.zip contains all my libraries, including taskswitching and dynamic vp loading.

The test program is a working demo how tasks and vp code work together.
TASK routines control·queues for vp code, whereas mainlevel code controls
the same queues but in the opposite direction. (eg. if mainlevel code fills a queue,
then a TASK subroutine empties it).

The VP definitions have been simplified and extended. The vpUart objects have now predefined
queues in their unoccupied space (a vpUart requires 10 bytes and the remaining 6 bytes are a queue).
You do not need to use the queues but the demo does use them.

Biggest problem was the fact that cc1b distinguishes two call trees: interrupt and mainlevel.
Because local variables are statically allocated at fixed addresses during compilation, a subroutine
with local variables cannot be called from both interrupt and mainlevel. The taskswitching adds another
call tree because taskcode can be interrupted by the interrupt. As far as cc1b is concerned, taskcode
is part of the interrupt call tree.

For this reason I had to rewrite the Portpin.h and objQueue.h libraries to support any call tree.
The Portpin.h library now consists mainly of macros but that does allow port and pin manipulations
from both mainlevel and tasklevel code using the same functions. (The alternative was to copy and rename
functions but that would increase codesize and is not very attractive).

The test program is a simple bidirectional uart, communicating at 9600 baud, 7 databits, 2 stopbits,
even parity. Note that the receive uart has inverted mode specified. This is because of the
simple RS232 interface.

Next step is to really use dynamic vp loading by stopping and starting vp's but for that
I need first to setup a board with a max232 for 4 rs232 lines.

regards peter