Wake-up Timer..... Inconsistent Documentation

pjv

Hello Parallax;

The on-line documentation for the SX48 states on page 17 that the shortest· DRT timer (FUSEX bits 1:0 set to 1,0) is 0.6 microSeconds..... nice and snappy.· Furter down in the docs on page 40 it states that the fastest setting is 0.25 mSec. Which one is correct??
The other three choices are consistent.

Also, the docs for the SX20/28 on·page 29 references a similar two bit selection for the DRT timer, when no such option actually appears to exist. This is a bit misleading, and ought to be straightened out.

Post Script......

Furthermore, the IDE's DEVICE window indicates a selection of 60 uSec for the DRT, and it should·read 250 uSec.

Cheers,

Peter (pjv)


Post Edited (pjv) : 8/31/2007 11:00:21 PM GMT

pjv

Hi All;

Because it's important to an ultra low power project I'm working on, I thought I'd pursue some of the finer points of the SX28 and SX48 regarding sleep modes.

At room temperature and 5 Volts:

Here are some points on the SX28:

1. During sleep the output registers levels (hi or lo) are maintained
2. During sleep the clock stops running.
3. The port direction registers are forced to INPUT direction on exit from sleep because a RESET condition is issued.
4. With a program running (not sleeping), then holding MCLR low ceases further instructions, but the clock keeps running.
5. Release of the MCLR initiates the reset.
6. On release of MCLR there is an approximate 16 millisecond duration (DRT) when no instructions are executed.
7. If power is applied simultaneous with releasing the MCLR (normally the case as the MCLR line is usually pulled up to V+), there is an approximate 60 millisecond period before any instructions are executed.
8. These times are independent of oscillator settings, internal/external, or frequency settings.

And for the SX48:

1. During sleep the output registers levels (hi or lo) are maintained
2. During sleep the clock can be configured to·keep running (Sleep clock option). This consumes extra power over the non clocking sleep condition of 50-ish uA at 5 Volts, depending on the oscillator settings:
HS3 @50MHz + 35 mA; HS2 @50 MHz + 28 mA; HS1 @50MHz + 11 mA; XT2 @ 4MHz + 4 mA; XT1 @4 MHz + 300 uA; LP2 & LP1 will not run with a 4 mHZ resonator.
Internal oscillator 32KHz through 4 MHz (all settings) + 1 mA.
3. The port direction registers are forced to INPUT direction on exit from sleep because a RESET condition is issued.
4. With a program running (not sleeping), then holding MCLR low ceases further instructions, but the clock keeps running.
5. Release of the MCLR initiates the reset.
6. On release of MCLR there are 4 selectable DRT durations when no instructions are executed; approximately 250 uSec, 16 mSec, 60 mSec, 960 mSec
7. If power is applied simultaneous with releasing the MCLR (normally the case as the MCLR line is usually pulled up to V+), there is a minimum period of·approximate 60 millisecond period before any instructions are executed.
8. These times are independent of oscillator settings, internal/external, or frequency settings.

It seems the SX48 is the best choice of the two as it will start executing in 250 uSec after exit from sleep, even with the clock stopped, whereas the best for an SX28 is·16 mSec. for the same conditions.

Hope this may be of use to some who are trying to run things on low power.

Cheers,

Peter (pjv)

Post Edited (pjv) : 8/31/2007 10:55:56 PM GMT

Bean

Peter,
Thanks for the info. Do you know if the execution time is shorter on the SX48 if you keep the clock running ?

Bean.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
The first rule to being successful is "Learn from your mistakes",
The second rule is "Be willing to make mistakes"
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
www.hittconsulting.com
·

pjv

Hi Bean,

No, it's the same.

I expect the reason for the delays are to let the oscillators' frequencies stabilize, but in practice it probably doesn't have much impact over such a short interval.

Cheers,

Peter (pjv)

Tracy Allen

I have a little note on the wakeup process in the BS2pe at this URL:

www.emesystems.com/BS2pe.htm#shortstart

The BS2pe is the only Stamp that uses the minimal DRT, so it can cut down the average current in apps that spend a lot of time sleeping.

With respect to MCLR, note that Reset not a low power state. As Peter pointed out, the clock continues and the chip draws its operating power. Same for brownout, the chip draws full power. So if a system is operating from a marginal battery, an external reset or brownout will not slow further drain from the battery.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com