_CLKMODE used with pll4x problems

R Pankau

I've been banging my head on this one for two days now.··· Thought it was solved months ago but I'm building a frugal mans prop-plug with the schematic with transistors.··

Using Pin 30 to transmit serial data I finally was able to get garbage on my teraterm, that was a giant leap.
The interesting part is that if·I use _CLKMODE·+ pll4x with a 20MHz crystal it puts garbage out.· but if the multiplier is left off and I just use 20MHZ it works well.··

The serial object is "FullDuplex" as far as I can tell it does all timing calcs by using this bit of code
· bit_ticks := clkfreq / baudrate

so why should it matter that the clkfreq is 80MHz instead of 20?· i thought I was giving the processor some head-room with the bump to 80MHz.··

Maybe I'm using _CLKMODE incorrectly?·· Hitting F8 tells me that clock mode, clock freq, and XIN freq are all what I expect to see, except that it doesn't work.

Here is my CON section
· _clkmode····· = XTAL3 + pll4x········ 'Leave pll4x·off and it works.·
· _xinfreq····· = 20_000_000

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
I'd rather have a bottle in front of me than a frontal labotomy

deSilva

A PLL will work within a specific range only . 20 MHz is definitely out! It's not so touchy WRT low frequencies are but there is a limit too. See the Data Sheet!

R Pankau

Hmmmm that may be it.· page 16 says 4 to 8 MHz with PLL running.·

good call.·· I guess that's why all examples use the 5MHZ crystal as it allow one to get to 80 and anything in-between.··



thanks.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
I'd rather have a bottle in front of me than a frontal labotomy

hippy

Somewhere in the Manual it explains that whenever PLL is enabled the crystal frequency is always multiplied by 16 and then the _CLKMODE PLL specifier selects what division of that to use. The problem here is that 20MHz x 16 exceeds the maximum operating frequency before it is divided down by four.