TLC2543 and the Prop

Newzed

I am trying to read a TLC2543 with my Proto Board and am getting some weird goings-on.· This ADC module works perfectly with my Stamp, but when I hooked it up to the Proto and loaded the program, it took about 50 or 60 iterations of the read process before the reading stabilized.· It wasn't jittery or anything like that - it started out displaying a low value and slowly and steadily increased to the reading I was expecting.· After it reaches the correct reading it appears to be stable, althiough I am still testing that.· If I change the program and reload it, or even if I just reload it, it goes thru the "priming" process all over again.· Can anyone suggest a reason it takes the ADC so long to reach the proper value with the Prop?

I have attached the program.· The readadc method is at Line 134, the shiftin at Line 162 and the shiftout at Line 208.

Sid





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janb

Hi,
have you compared timing?
Prop is much faster than stamp. Is the·clocking in both cases comparable?
Have you tried to slow down proplleler, e.g. ·by adding waitcnt() ?
Or high state is marginal (prop is runing on 3.3 V) - this would better matched the description, sth is slowly charging up w/ prop and finaly it works. Try to measure volatges.
Pure speculation
Jan
·

Newzed

Jan, what is sth?

sth is slowly charging up

The 2543 is running at 5VDC and I have 4.7K in series with Dout to protect the Prop.

I read the ADC after about a 45 minute wait and it was right on.

Sid

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Yesterday is history, tomorrow is a mystery, and today is a gift.

That is why they call it the present.

Don't have VGA?
Newzed@aol.com
·

whicker

pin 18: IOCLOCK looks like it has some weird side effects:

1.It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK
with the multiplexer address available after the fourth rising edge.

2.On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input
begins charging the capacitor array and continues to do so until the last falling edge of the I/O
CLOCK.

3.It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on
the falling edge of I/O CLOCK.

4.It transfers control of the conversion to the internal state controller on the falling edge of the last
I/O CLOCK.


Perhaps you're not clocking enough, or are clocking asymmetrically?
You remembered to connect Ref+ and -?