Very neat indeed, and the "proper" way to do things.
I have previously experimented with your technique of using a low output pin as a "ground" and a high output pin as a "supply" to power a low current 4 legged strain bridge in order to get rid of emf developed in the SX power and ground bonding wires, and "ground bounce". But my results were less than satisfacory, in fact, poorer than the "normal" connection. Now, that said, I also had the low side of one of these R/C ADC capacitors connected to the "virtual" ground when I did these tests.
When the poor results were observed, I reasoned that the "ground" could only sink current (that's OK when the A/D is charging the cap), but could not source current when the A/D was discharging the cap. After all, the "schematics" of the silicon output pin only show an up pulling transistor and a down pulling transistor, and both of those are never on at the same time. But I know very little about the innards of IC's so the actual configuration may be different from the "equivalent" schematic.
If this concept of pulling current out of the bottom "on" transistor is indeed legitimate (I might have had some other issues I did not pursue), then I would really like to visit this again as it could be a great way to do instrumentation bridge measurements with a minimal of components............. allways a passion of mine.
Please advise on the legitimacy if you can confirm this.
If I get some time, I'll run a couple of tests to see how different connections affect the result.
My understanding of nMOS and pMOS transistors is that when they are "closed", they are like resistors and can pass current in either direction. That is the basis of analog switches. In the SX chip they are something like 30 ohms output resistance. You are right, the current does have to pass in both directions. It is not a large current, as the feeback current is basically 2.5 volts in series with (in this case) a 330kohm resistor. The voltage across the 30 ohm output resistance won't get anywhere near the threshold of the protection diodes.
I've used that kind of connection through pins in a dual slope scheme for a charge transfer converter. By reversing the high/low state of the two pins, it could charge the sampling capacitor in either direction. Then the sampling capacitor was isolated from the source and the charge was then transfered to a grounded integration capacitor thru another pair of analog switches. The integration capacitor was hooked to the (-) comparator input, while the comparator output and (+) input were hooked up to make a window. By changing the charge direction on the sampling capacitor, the integration could go both up and down.
Thanks for the response and your interest in this subject. A very clever idea of implementing the charge transfer.
True, the capacitor's current in my case is very small, still my results were quite poor. So perhaps there was something else afoot, and I was too quick to blame the wrong thing........ (slaps himself)! More study is required here on my part.
I suppose one could always switch in a bias current, but now it's starting to get a little hairy.
The stability is now greatly improved! Thank you so much!
Peter, I carefully read your comments about what I was doing wrong. It all makes sense to me now… but I really do not think I would have ever figured it out on my own.
I altered the changes you posted to work with the pins I am using. At the moment I am also running it at 20MHz. Do I need to use 50MHz?
Presently I have only tried your changes on my SX-Tech test setup. However, it makes sense what you said and I have seen an immediate improvement already!
Tracy, I am keeping your connection recommendations in mind. This will be going onto a custom PCB. So I will keep the parts close and the leads short as you suggest.
Thanks to both Peter and Tracy who offered many, many suggestions and to the others who offered recommendations as well. Special thanks especially to Peter who went out of his way to find errors that I could not see and even offered to send me a fully built and working project board.
For the benefit of those who have been following this thread and for those who may find it later, I am including the following attachments:
TEST-ADC-UART-03.SXB <--- Same basic program as TEST-ADC-UART-02.SXB but includes the changes Peter pointed out were necessary in his “Modified PJV test-adc-uart-02.SRC” file.
TEST-ADC-UART-02.jpg <--- Screen capture of the output from my test setup generated by the TEST-ADC-UART-02.SXB code.
TEST-ADC-UART-03.jpg <--- Screen capture of the output from my test setup generated by the TEST-ADC-UART-03.SXB code.
Thanks again to everyone for all the help!!! I might be posting again later but for now I think I am definitely headed off in the right direction.
Regarding 20 vs 50 MHz; when I ran the tests, it was at 20 MHz because the SX-Key uses the speed selected with the FREQ directive, and that was 20 MHz in your code.
You could opt for the higher speed, and that would permit proprtionally faster (shorter) RC time constant....... ie smaller capacitor, and hence it could follow input variations of a somewhat higher speed, say 5 or 10 mSec instead of the current 20 mSec.
Comments
Very neat indeed, and the "proper" way to do things.
I have previously experimented with your technique of using a low output pin as a "ground" and a high output pin as a "supply" to power a low current 4 legged strain bridge in order to get rid of emf developed in the SX power and ground bonding wires, and "ground bounce". But my results were less than satisfacory, in fact, poorer than the "normal" connection. Now, that said, I also had the low side of one of these R/C ADC capacitors connected to the "virtual" ground when I did these tests.
When the poor results were observed, I reasoned that the "ground" could only sink current (that's OK when the A/D is charging the cap), but could not source current when the A/D was discharging the cap. After all, the "schematics" of the silicon output pin only show an up pulling transistor and a down pulling transistor, and both of those are never on at the same time. But I know very little about the innards of IC's so the actual configuration may be different from the "equivalent" schematic.
If this concept of pulling current out of the bottom "on" transistor is indeed legitimate (I might have had some other issues I did not pursue), then I would really like to visit this again as it could be a great way to do instrumentation bridge measurements with a minimal of components............. allways a passion of mine.
Please advise on the legitimacy if you can confirm this.
Cheers,
Peter (pjv)
If I get some time, I'll run a couple of tests to see how different connections affect the result.
My understanding of nMOS and pMOS transistors is that when they are "closed", they are like resistors and can pass current in either direction. That is the basis of analog switches. In the SX chip they are something like 30 ohms output resistance. You are right, the current does have to pass in both directions. It is not a large current, as the feeback current is basically 2.5 volts in series with (in this case) a 330kohm resistor. The voltage across the 30 ohm output resistance won't get anywhere near the threshold of the protection diodes.
I've used that kind of connection through pins in a dual slope scheme for a charge transfer converter. By reversing the high/low state of the two pins, it could charge the sampling capacitor in either direction. Then the sampling capacitor was isolated from the source and the charge was then transfered to a grounded integration capacitor thru another pair of analog switches. The integration capacitor was hooked to the (-) comparator input, while the comparator output and (+) input were hooked up to make a window. By changing the charge direction on the sampling capacitor, the integration could go both up and down.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com
Thanks for the response and your interest in this subject. A very clever idea of implementing the charge transfer.
True, the capacitor's current in my case is very small, still my results were quite poor. So perhaps there was something else afoot, and I was too quick to blame the wrong thing........ (slaps himself)! More study is required here on my part.
I suppose one could always switch in a bias current, but now it's starting to get a little hairy.
I look forward to the results of your tests.
Cheers,
Peter (pjv)
The stability is now greatly improved! Thank you so much!
Peter, I carefully read your comments about what I was doing wrong. It all makes sense to me now… but I really do not think I would have ever figured it out on my own.
I altered the changes you posted to work with the pins I am using. At the moment I am also running it at 20MHz. Do I need to use 50MHz?
Presently I have only tried your changes on my SX-Tech test setup. However, it makes sense what you said and I have seen an immediate improvement already!
Tracy, I am keeping your connection recommendations in mind. This will be going onto a custom PCB. So I will keep the parts close and the leads short as you suggest.
Thanks to both Peter and Tracy who offered many, many suggestions and to the others who offered recommendations as well. Special thanks especially to Peter who went out of his way to find errors that I could not see and even offered to send me a fully built and working project board.
For the benefit of those who have been following this thread and for those who may find it later, I am including the following attachments:
TEST-ADC-UART-03.SXB <--- Same basic program as TEST-ADC-UART-02.SXB but includes the changes Peter pointed out were necessary in his “Modified PJV test-adc-uart-02.SRC” file.
TEST-ADC-UART-02.jpg <--- Screen capture of the output from my test setup generated by the TEST-ADC-UART-02.SXB code.
TEST-ADC-UART-03.jpg <--- Screen capture of the output from my test setup generated by the TEST-ADC-UART-03.SXB code.
Thanks again to everyone for all the help!!! I might be posting again later but for now I think I am definitely headed off in the right direction.
- Sparks
I'm glad it's now working for you.
Regarding 20 vs 50 MHz; when I ran the tests, it was at 20 MHz because the SX-Key uses the speed selected with the FREQ directive, and that was 20 MHz in your code.
You could opt for the higher speed, and that would permit proprtionally faster (shorter) RC time constant....... ie smaller capacitor, and hence it could follow input variations of a somewhat higher speed, say 5 or 10 mSec instead of the current 20 mSec.
Cheers,
Peter (pjv)