Changes to Large Memory Model
Bill Henning
Posts: 6,445
Hi guys,
My consulting is slowing down a bit, so I've started working on the large model again. After due consideration, I've made a few changes to the architecture:
Here is the revised cog memory map:
$000-$07F The large model pico-kernel
$080-$0FF FCACHE buffer (as before)
$100-$17F DCACHE buffer (to be documented)
$180-$1DF global “register” variable area, shared by all the threads
$1E0-$1EF virtual machine registers
$1F0-$1FF Propeller special purpose registers
This is compatible with the previous map, except the different sections are a bit more clearly defined.
Here are the virtual machine registers:
$1E0 PC Program Counter
$1E1 SP Stack Pointer
$1E2 BP Base Pointer
$1E3 FLAGS Reserved for multi-threaded version of kernel
$1E4 R0 General Purpose Register - Accumulator
$1E5 R1 General Purpose Register
$1E6 R2 General Purpose Register
$1E7 R3 General Purpose Register
$1E8 R4 General Purpose Register
$1E9 R5 General Purpose Register
$1EA R6 General Purpose Register
$1EB R7 General Purpose Register
$1EC R8 General Purpose Register
$1ED R9 General Purpose Register
$1EE R10 General Purpose Register
$1EF R11 General Purpose Register
I am afraid that due to memory constraints, I've had to make R0 be a bit special, and I removed the multi-threading specific registers in order to give a few more general purpose registers (R8-R11) to compiler generated code.
Here is the jump table at the start of the kernel:
$000 @NEXT
$001 @FJMP
$002 @FCALL
$003 @FRET
$004 @FLDI
$005 @FPUSHI
$006 @FPUSH
$007 @FPOP
$008 @FCACHE
$009 @FYIELD
$00A @FSVC
$00B @FLIB
I've added a few new opcodes, namely:
FPUSHI const32 pushes 32 bit constant onto the return stack
FPUSH pushes R0 onto the return stack
FPOP pops from the return stack into R0
These additions are meant to make it easier to pass parameters to compiler generated code. It would be possible to make FPUSH/FPOP be more generic, capable of pushing/popping any cog register, but I don't think it is worth the cycles or words of cog memory required to implement that flexibility.
The assembler I am working on will support the large model opcodes, but for now you can just use
jmp 1 ' same os FJMP
jmp 2 ' same as FCALL
jmp 3 ' same as FRET
etc etc etc
And horror of horrors... I've started the first of a series of articles documentiong the large mode.
Sorry for the delay guys, I've been working crazy hours.
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www.mikronauts.com - a new blog about microcontrollers
My consulting is slowing down a bit, so I've started working on the large model again. After due consideration, I've made a few changes to the architecture:
Here is the revised cog memory map:
$000-$07F The large model pico-kernel
$080-$0FF FCACHE buffer (as before)
$100-$17F DCACHE buffer (to be documented)
$180-$1DF global “register” variable area, shared by all the threads
$1E0-$1EF virtual machine registers
$1F0-$1FF Propeller special purpose registers
This is compatible with the previous map, except the different sections are a bit more clearly defined.
Here are the virtual machine registers:
$1E0 PC Program Counter
$1E1 SP Stack Pointer
$1E2 BP Base Pointer
$1E3 FLAGS Reserved for multi-threaded version of kernel
$1E4 R0 General Purpose Register - Accumulator
$1E5 R1 General Purpose Register
$1E6 R2 General Purpose Register
$1E7 R3 General Purpose Register
$1E8 R4 General Purpose Register
$1E9 R5 General Purpose Register
$1EA R6 General Purpose Register
$1EB R7 General Purpose Register
$1EC R8 General Purpose Register
$1ED R9 General Purpose Register
$1EE R10 General Purpose Register
$1EF R11 General Purpose Register
I am afraid that due to memory constraints, I've had to make R0 be a bit special, and I removed the multi-threading specific registers in order to give a few more general purpose registers (R8-R11) to compiler generated code.
Here is the jump table at the start of the kernel:
$000 @NEXT
$001 @FJMP
$002 @FCALL
$003 @FRET
$004 @FLDI
$005 @FPUSHI
$006 @FPUSH
$007 @FPOP
$008 @FCACHE
$009 @FYIELD
$00A @FSVC
$00B @FLIB
I've added a few new opcodes, namely:
FPUSHI const32 pushes 32 bit constant onto the return stack
FPUSH pushes R0 onto the return stack
FPOP pops from the return stack into R0
These additions are meant to make it easier to pass parameters to compiler generated code. It would be possible to make FPUSH/FPOP be more generic, capable of pushing/popping any cog register, but I don't think it is worth the cycles or words of cog memory required to implement that flexibility.
The assembler I am working on will support the large model opcodes, but for now you can just use
jmp 1 ' same os FJMP
jmp 2 ' same as FCALL
jmp 3 ' same as FRET
etc etc etc
And horror of horrors... I've started the first of a series of articles documentiong the large mode.
Sorry for the delay guys, I've been working crazy hours.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
www.mikronauts.com - a new blog about microcontrollers