Yes, I'm building an auxillary navigation controller for robotic applications.
My goal is to connect two propellers to the ram card and have it act as a shared
memory and obviously giving them both more ram.
I'll try to look for the interface spec on the forum.
I tried searching with the forum search, but it can't seem to find it. I uploaded the whole chapter on the expansion interface for the hydra, really short like 5 pages, that's it. So maybe someone is better at searching with this forum.
But, anyway, just set aside 8 lines for the data/address bus, and 3 lines for the control. And you need power of course, ground, and the reset line goes to my controller as well.
That will be cool though with the memory between a couple of them. The next propeller project I will make is tentatively called the "HYDRA Nemesis", 4 propellers, shared SRAM basically.
Since I'm going to be sharing the SRAM interface between two props on the same bus, I was thinking that control of the strobe pin might be an issue.
How does the strobe pin work to signal the SRAM. I'd kindof assume it strobes when pulled low or something, but I want to be certain.
Also when in the control sequence does the SRAM set its IO to inputs and outputs?
Only when the strobe is taken high low high, do things happens. So during "setup" you can set the io's on the data bus to input or output and set them, the controll lines though are always output, so you want to keep those outputs.
So the order of operations is:
1. Reset the computer
2. Write the initialization program to the SRAM controller (one time deal every reset)
3. initialize your IO so that the data bus is an input, control and strobe output, everything low
4. begin operation
for every opertation, set the control to what you want, set the data bus to in or out (put data on bus if out operation)
I am curious how the programming of the SRAM controller (CPLD) is performed.
Am I correct in assuming that after power on the CPLD is not yet programmed (empty), and that the application running on the Propeller has to program it before it can be used?
In that case how is the physical interface done to program the CPLD, through the same 8-data-bit + 3-control-bit lines?
KISS man KISS. When it boots, the first thing you write to it is the "program", then that dictates the auto inc/dec behavior from there.
Andre'
PUB SRAM_WriteControl_S( _data8 )····
' this function writes the intial control word to the controller · ' set global address · sram_addr := 0 · sram_data := _data8 · ' set bus to write · DIRA[noparse][[/noparse] SRAM_IO_7..SRAM_IO_0 ]···· := $FF ' $FF ouput, $00 input · ' output control byte · OUTA[noparse][[/noparse] SRAM_IO_7..SRAM_IO_0 ]···· := sram_data ··· · ' set control bits for load low memory address, doesn't matter what operation really · DIRA[noparse][[/noparse] SRAM_CTRL_1..SRAM_CTRL_0 ] := $03··········· ' set to outputs · OUTA[noparse][[/noparse] SRAM_CTRL_1..SRAM_CTRL_0 ] := %000000_00
· ' now strobe sram clk line · DIRA[noparse][[/noparse] SRAM_STROBE ]············· := $01··········· ' set to outputs · OUTA[noparse][[/noparse] SRAM_STROBE ]············· := $00 · OUTA[noparse][[/noparse] SRAM_STROBE ]············· := $01 · OUTA[noparse][[/noparse] SRAM_STROBE ]············· := $00· · ' needed to interact properlly with ASM driver for now · OUTA[noparse][[/noparse] SRAM_CTRL_1..SRAM_CTRL_0 ] := %000000_00 · DIRA[noparse][[/noparse] SRAM_IO_7..SRAM_IO_0 ]···· := $00 ' $FF ouput, $00 input · ' return data to caller · return(sram_data)
I thought that CPLD's could hold a program. If I have read correctly, CPLDs are flash programmable; FPGAs however need to be programmed by a host each startup before they are used.
Looking at the picture, it looks as if the programming lines are brought out to a seperate header.
Andre', KISS (keep it simple s****d) is my guiding principle when designing anything.
Larry, at the moment I am a bit confused about what actually happens at boot time with the CPLD.
I am well aware that most CPLD's are flash programmable, using a set of special interface/programming pins brought out to a header with which you can program the device, (often using a parallel printer port).
In contrast most FPGA's have a "self load" mechanism, and read their "program" from an external serial EEPROM at power on, but thats another issue.
However, in an earlier thread Andre' said;
Andre' said...
You load a program into the CPLD at boot that describes the behavior, and other than using sequencial states to load all 19 bits, there aren't enough i/o lines to do it.
That seems to imply the CPLD's behavior can be "changed" at boot (power on) time.
So I assumed there is some mechanism programmed into the CPLD (at flash programming time) that after power-on waits for some "parameters" (or something) from the propeller to "configure" the RAM-access mechanism. I assume this is how you "tell" the CPLD that the controller does an auto increment, auto decrement, or nothing, after each memory access. At least, that is what I gathered from some remarks Andre' made in the same earlier thread.
How the memory above 64K can be reached without the auto increment mechanism is also a puzzle, but thats also another issue.
And Andre' also seems to also imply the same with:
Andre' said...
When it boots, the first thing you write to it is the "program", then that dictates the auto inc/dec behavior from there
However the program in Andre's last message seems to be the code (which seems to be just a simple "set low address" command) to write a "control word" to the CPLD at boot-up.
But it does not describe the control word itself and what it configures.
So my question to Andre' still is:
What exactly do you have to write to the CPLD to change the behavior, and what exactly can be configured in the memory access protocol.
Only the inc/dec behavior?
The CPLD is a flash device. You program it whenever you want with a flash programmer via a header. Simple. Its comes pre-programmed so its a SRAM controller.
The "program" you send to the SRAM controller on boot describes how you want the SRAM controller to operate. Its a single byte.
If you want to re-program the CPLD, then you need to learn ABEL, or VERILOG or VHDL, get a programmer (or build one with the diagram I supply) install the tool, write your code, compile your code, download to the part via the standard interface cable that you buy or you build.
Is it possible to post the diagram for the CPLD programmer so I can start building it...
Sounds awesome, cant wait to get my hands on the card...
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Living on the planet Earth might be expensive but it includes a free trip around the sun every year...
Experience level:
[noparse][[/noparse] ] Let's connect the motor to pin 1, it's a 6V motor so it should be fine.
[noparse][[/noparse] ] OK, I got my resistors hooked up with the LEDs.
[noparse][[/noparse]X] I got the Motor hooked up with the H-bridge and the 555 is supplying the PWM.
[noparse][[/noparse] ] Now, if I can only program the BOE-BOT to interface with he Flux Capacitor.
[noparse][[/noparse] ] I dream in SX28 assembler...
It only takes a couple hours to build if that. Its a standard Lattice ISP programmer, you can find schematics online. The biggest problem is making the connections to the parallel cable, you have to strip the lines, do a lot of mechanical and solder, pain in the butt stuff.
My new computer doesn't even have a Parallel port...
Guess I have to buy the $30 Parallel port card or dust off my old computer...
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Living on the planet Earth might be expensive but it includes a free trip around the sun every year...
Experience level:
[noparse][[/noparse] ] Let's connect the motor to pin 1, it's a 6V motor so it should be fine.
[noparse][[/noparse] ] OK, I got my resistors hooked up with the LEDs.
[noparse][[/noparse]X] I got the Motor hooked up with the H-bridge and the 555 is supplying the PWM.
[noparse][[/noparse] ] Now, if I can only program the BOE-BOT to interface with he Flux Capacitor.
[noparse][[/noparse] ] I dream in SX28 assembler...
OR just buy the USB programmer. But ,yes, every computer should have a parallel port especially if you're going to do hardware. Its a great IO device. I Always make sure all new pcs I buy have 1.
Ok, after exaustive testing of the sram, looks like its good to go, in a couple weeks, I can't get a single bad read/write, no matter how fast I push it. The ASM and SPIN drivers are done, cleaning them up now. I will start the manufacturing process next week, BUT I will do some local manufacturing with local american labor to get some boards ready asap ($$$$$$$$$$$$$$$), so we don't have to wait for the chinese, sometimes it takes 6-8 weeks to get things rolling with them.
So once I wrap this up, then I will write the API docs, a simple memory pass/fail demo that exercises the functions for an example in both spin and ASM and maybe some kind of slow graphics demo that interfaces to the SRAM and moves things around. If I get time I will make a new bitmapped video driver that uses it, we will see, but better to get this out there asap, then someone else can do it [noparse]:)[/noparse]
Anyway, still looks around $39-49 for the board to start with and we will go from there. This should really transform the HYDRA into a complete personal computer that with some good programming a really rich BASIC or other HLL can run on it and plug into the TV which was my initial goal.
Andre' said...
The CPLD is a flash device. You program it whenever you want with a flash programmer via a header. Simple. Its comes pre-programmed so its a SRAM controller.
The "program" you send to the SRAM controller on boot describes how you want the SRAM controller to operate. Its a single byte.
If you want to re-program the CPLD, then you need to learn ABEL, or VERILOG or VHDL, get a programmer (or build one with the diagram I supply) install the tool, write your code, compile your code, download to the part via the standard interface cable that you buy or you build.
Andre'
I understood all that, my only remaining question was, what actually can this single byte change in the operation of the SRAM controller?
let me do a wild guess, just to show what kind of answer I expected to hear from you:
* 00H = no increment/decrement after a memory access
* 01H = increment after a memory access
* 02H = decrement after a memory access
* 03H to FFH invalid.
An answer like this is all I wanted to know at this point.
[noparse][[/noparse]quote user=Andre']Anyway, still looks around $39-49 for the board to start with and we will go from there. This should really transform the HYDRA into a complete personal computer that with some good programming a really rich BASIC or other HLL can run on it and plug into the TV which was my initial goal.
That would be awesome Never thought of using it as program space.
Anyway, how much EEPROM will be on this thing? I assume 128K as per usual.
it will have the 128K and the 512K SRAM, so basically 4X as much rom space as any 8-bit computer and about 16x as much ram as any 8-bit computer from the 80's.
Comments
Yes, I'm building an auxillary navigation controller for robotic applications.
My goal is to connect two propellers to the ram card and have it act as a shared
memory and obviously giving them both more ram.
I'll try to look for the interface spec on the forum.
-Chad
But, anyway, just set aside 8 lines for the data/address bus, and 3 lines for the control. And you need power of course, ground, and the reset line goes to my controller as well.
That will be cool though with the memory between a couple of them. The next propeller project I will make is tentatively called the "HYDRA Nemesis", 4 propellers, shared SRAM basically.
Andre'
' SRAM bus interface pin constants
SRAM_CTRL_0 = 1 ' NET_RX_CLK (expansion pin 10)
SRAM_CTRL_1 = 2 ' NET_TX_DATA (expansion pin 9)
SRAM_STROBE = 30 ' USB_RXD (Prop TX ----> USB_RXD Host) (expansion pin 19)
SRAM_IO_7 = 23 ' IO_7 (pin 28)
SRAM_IO_6 = 22
SRAM_IO_5 = 21
SRAM_IO_4 = 20
SRAM_IO_3 = 19
SRAM_IO_2 = 18
SRAM_IO_1 = 17
SRAM_IO_0 = 16 ' IO_0 (pin 21)
Andre'
Since I'm going to be sharing the SRAM interface between two props on the same bus, I was thinking that control of the strobe pin might be an issue.
How does the strobe pin work to signal the SRAM. I'd kindof assume it strobes when pulled low or something, but I want to be certain.
Also when in the control sequence does the SRAM set its IO to inputs and outputs?
Thanks,
Chad
So the order of operations is:
1. Reset the computer
2. Write the initialization program to the SRAM controller (one time deal every reset)
3. initialize your IO so that the data bus is an input, control and strobe output, everything low
4. begin operation
for every opertation, set the control to what you want, set the data bus to in or out (put data on bus if out operation)
Pulse strobe
Retrieve data from bus if a read operation.
That's it, simple.
Andre'
http://forums.parallax.com/forums/attach.aspx?a=12637
But, its about 4.5cm x 6cm tall (not counting the header edge plugged into the interface)
Andre'
Am I correct in assuming that after power on the CPLD is not yet programmed (empty), and that the application running on the Propeller has to program it before it can be used?
In that case how is the physical interface done to program the CPLD, through the same 8-data-bit + 3-control-bit lines?
Mahjongg
Andre'
PUB SRAM_WriteControl_S( _data8 )····
' this function writes the intial control word to the controller
· ' set global address
· sram_addr := 0
· sram_data := _data8
· ' set bus to write
· DIRA[noparse][[/noparse] SRAM_IO_7..SRAM_IO_0 ]···· := $FF ' $FF ouput, $00 input
· ' output control byte
· OUTA[noparse][[/noparse] SRAM_IO_7..SRAM_IO_0 ]···· := sram_data
···
· ' set control bits for load low memory address, doesn't matter what operation really
· DIRA[noparse][[/noparse] SRAM_CTRL_1..SRAM_CTRL_0 ] := $03··········· ' set to outputs
· OUTA[noparse][[/noparse] SRAM_CTRL_1..SRAM_CTRL_0 ] := %000000_00
· ' now strobe sram clk line
· DIRA[noparse][[/noparse] SRAM_STROBE ]············· := $01··········· ' set to outputs
· OUTA[noparse][[/noparse] SRAM_STROBE ]············· := $00
· OUTA[noparse][[/noparse] SRAM_STROBE ]············· := $01
· OUTA[noparse][[/noparse] SRAM_STROBE ]············· := $00·
· ' needed to interact properlly with ASM driver for now
· OUTA[noparse][[/noparse] SRAM_CTRL_1..SRAM_CTRL_0 ] := %000000_00
· DIRA[noparse][[/noparse] SRAM_IO_7..SRAM_IO_0 ]···· := $00 ' $FF ouput, $00 input
· ' return data to caller
· return(sram_data)
Looking at the picture, it looks as if the programming lines are brought out to a seperate header.
Andre', KISS (keep it simple s****d) is my guiding principle when designing anything.
Larry, at the moment I am a bit confused
I am well aware that most CPLD's are flash programmable, using a set of special interface/programming pins brought out to a header with which you can program the device, (often using a parallel printer port).
In contrast most FPGA's have a "self load" mechanism, and read their "program" from an external serial EEPROM at power on, but thats another issue.
However, in an earlier thread Andre' said;
That seems to imply the CPLD's behavior can be "changed" at boot (power on) time.
So I assumed there is some mechanism programmed into the CPLD (at flash programming time) that after power-on waits for some "parameters" (or something) from the propeller to "configure" the RAM-access mechanism. I assume this is how you "tell" the CPLD that the controller does an auto increment, auto decrement, or nothing, after each memory access. At least, that is what I gathered from some remarks Andre' made in the same earlier thread.
How the memory above 64K can be reached without the auto increment mechanism is also a puzzle, but thats also another issue.
And Andre' also seems to also imply the same with:
However the program in Andre's last message seems to be the code (which seems to be just a simple "set low address" command) to write a "control word" to the CPLD at boot-up.
But it does not describe the control word itself and what it configures.
So my question to Andre' still is:
What exactly do you have to write to the CPLD to change the behavior, and what exactly can be configured in the memory access protocol.
Only the inc/dec behavior?
Mahjongg
The "program" you send to the SRAM controller on boot describes how you want the SRAM controller to operate. Its a single byte.
If you want to re-program the CPLD, then you need to learn ABEL, or VERILOG or VHDL, get a programmer (or build one with the diagram I supply) install the tool, write your code, compile your code, download to the part via the standard interface cable that you buy or you build.
Andre'
Sounds awesome, cant wait to get my hands on the card...
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Living on the planet Earth might be expensive but it includes a free trip around the sun every year...
Experience level:
[noparse][[/noparse] ] Let's connect the motor to pin 1, it's a 6V motor so it should be fine.
[noparse][[/noparse] ] OK, I got my resistors hooked up with the LEDs.
[noparse][[/noparse]X] I got the Motor hooked up with the H-bridge and the 555 is supplying the PWM.
[noparse][[/noparse] ] Now, if I can only program the BOE-BOT to interface with he Flux Capacitor.
[noparse][[/noparse] ] I dream in SX28 assembler...
/Bamse
Andre'
http://elm-chan.org/works/avrx/lattice.png
My new computer doesn't even have a Parallel port...
Guess I have to buy the $30 Parallel port card or dust off my old computer...
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Living on the planet Earth might be expensive but it includes a free trip around the sun every year...
Experience level:
[noparse][[/noparse] ] Let's connect the motor to pin 1, it's a 6V motor so it should be fine.
[noparse][[/noparse] ] OK, I got my resistors hooked up with the LEDs.
[noparse][[/noparse]X] I got the Motor hooked up with the H-bridge and the 555 is supplying the PWM.
[noparse][[/noparse] ] Now, if I can only program the BOE-BOT to interface with he Flux Capacitor.
[noparse][[/noparse] ] I dream in SX28 assembler...
/Bamse
Andre'
So once I wrap this up, then I will write the API docs, a simple memory pass/fail demo that exercises the functions for an example in both spin and ASM and maybe some kind of slow graphics demo that interfaces to the SRAM and moves things around. If I get time I will make a new bitmapped video driver that uses it, we will see, but better to get this out there asap, then someone else can do it [noparse]:)[/noparse]
Anyway, still looks around $39-49 for the board to start with and we will go from there. This should really transform the HYDRA into a complete personal computer that with some good programming a really rich BASIC or other HLL can run on it and plug into the TV which was my initial goal.
Andre'
I understood all that, my only remaining question was, what actually can this single byte change in the operation of the SRAM controller?
let me do a wild guess, just to show what kind of answer I expected to hear from you:
* 00H = no increment/decrement after a memory access
* 01H = increment after a memory access
* 02H = decrement after a memory access
* 03H to FFH invalid.
An answer like this is all I wanted to know at this point.
Mahjongg
Andre'
That would be awesome
Anyway, how much EEPROM will be on this thing? I assume 128K as per usual.
Andre'