Shop OBEX P1 Docs P2 Docs Learn Events
SX28 Output Pin state when placed in sleep mode? — Parallax Forums

SX28 Output Pin state when placed in sleep mode?

DavehamDaveham Posts: 2
edited 2007-03-06 18:04 in General Discussion
When the the SX28 is put into sleep mode do the pins assigned as outputs hold there present state·or are they made tri-state?

Thanks!
David.

Comments

  • BeanBean Posts: 8,129
    edited 2007-02-27 22:54
    David,
    They hold their last state.

    Bean.

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    Cheap used 4-digit LED display with driver IC·www.hc4led.com

    Low power SD Data Logger www.sddatalogger.com
    SX-Video Display Modules www.sxvm.com
    ·
  • dkemppaidkemppai Posts: 315
    edited 2007-03-04 01:35
    Hi,

    They do hold their state during a sleep cycle, but upon wakeup, they can loose
    their state.

    If you detect the source of the SX reset (from interrupt, or WDT, etc), and try
    to resume your code you can get into trouble. Don't count on the output pins
    being in the states you left them in after a wake up.

    Try a simple program that uses the WDT, a resistor and an LED.
    Set the WDT to wake the chip up every second or so, and determine
    the source of the reset. If the reset was the WDT, then read the
    state of the·output, and toggle the·output pin (with LED and resistor on it),
    and put the SX to sleep. Let the program run.

    What you would expect to get would be a 50% duty cycle square wave
    flashing the LED·on the output pin, but won't happen.·At least I couldn't
    get it to happen on my program. What happens is upon reset, the RA/B/C
    Data isn't changed, but the direction registers are forced to inputs...
    ...and I think that's where the problem is.

    Anway, have a look at http://www.parallax.com/dl/appnt/sx/An18Reset.pdf
    on page·3 there is a table showing what resets do to each respective
    register in the SX. It's the direction registers getting changed that can bite
    you.

    The workaround to this is to copy your output to registers, and upon wakeup
    restore their values. You may still get a glitch on any high outputs, tho...

    -Dan


    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔

    "A saint-like quantity of patience is a help, if this is unavailable, a salty vocabulary works nearly as well." - A. S. Weaver
  • DragonSXDragonSX Posts: 14
    edited 2007-03-06 18:04
    I have been looking for more information on the reset for the SX48BD. After getting my hopes up a little when it talked about "For fast start-up from the power down mode, clear the SLEEPCLK bit and set the WDRT2:WDRT0 field to 100." I noticed that this did not match the datasheet for the SX48BD. My datasheet specifies an 2-bit DRT field. Also, there seems to be differences in the minimum DRT time. One datasheet floating around says 250uS and another says 60uS. My experiments with the SX48BD seems to give me closer to 250uS.

    The doc dkemppai posted seems to have been dated year 2000. Was there a change in design at sometime? Is there anyway I can get the SX48BD to have zero startup delay?

    -Matt
Sign In or Register to comment.