What is the maximum frequency that can be counted using POSEDGE counter mode ?
Bean
Posts: 8,129
When clocking the propeller at 80MHz, what is the maximum frequency that can be counted using the POSEDGE mode·?
I read the counter app note, but it doesn't say. I assume it is some division of the propeller clock.
Bean.
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I read the counter app note, but it doesn't say. I assume it is some division of the propeller clock.
Bean.
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Comments
40 MHz (f/2)
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Chris Savage
Parallax Tech Support
Bean.
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"USA Today has come out with a new survey - apparently, three out of every four people make up 75% of the population." - David Letterman
Here's a diagram that illustrates how POSEDGE works as a state machine.
The input signal is sampled once on each master clock cycle (once every 12.5 nanoseconds for clkfreq=80mhz). The state machine looks at the two previous samples, and the result is the logical AND of the sample from one time period back with the NOT of the sample from two time periods back. Iff that is 1, then FRQx is added to PHSx. The diagram shows the advance of the counter PHSx assuming FRQx=1. Also it shows the input frequency at slightly less than 1/2 of the clkfreq, so there has to be instances where the result is 0 or 1 for two successive cycles of clkfreq in a row. But the count will always be correct so long as the input frequency is less than or equal to the clkfreq/2 ***AND*** the individual times low and high are at least 1/clkfreq in duration (12.5 ns with clkfreq=80mhz). Note that the count is delayed by two cycles of clkfreq.
I don't know really how the input is sampled. It is not an edge triggered latch, I think we do know that. My guess is that it is a level sensitive latch. Chip?
What happens when the condition is violated and the input frequency is between clkfreq/2 and clkfreq? It will miss pulses. However, it may be that over the long term it would still correctly acquire the average frequency of a symmetrical square wave, if that is the intent, when total count is divided by total time over a long duration.
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Tracy Allen
www.emesystems.com
My input is about 1/3 of the clock freq with a 45-55% duty cycle, so I should be fine.
I'm working on using the propeller in an MCXO oscillator, where a xtal is operated at it's fundamental AND 3rd overtone frequencies at the same time.
Bean.
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Post Edited (Bean (Hitt Consulting)) : 2/15/2007 6:28:50 PM GMT
My analysis of the situation was incorrect, see Chip's post below, sorry about that.
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Paul Baker
Propeller Applications Engineer
Parallax, Inc.
Post Edited (Paul Baker (Parallax)) : 2/15/2007 6:45:49 PM GMT
That would have had be screwed up for awhile.
Bean.
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"USA Today has come out with a new survey - apparently, three out of every four people make up 75% of the population." - David Letterman
It will be adding FRQ into PHS at 40MHz, since every other 80MHz clock·pulse will register an edge of interest.
for 0-to-1:
0··· captured 0
1··· captured 1 - edge detected, add FRQ into PHS
0··· captured 0
1··· captured 1 - edge detected, add FRQ into PHS
0··· captured 0
1··· captured 1 - edge detected, add FRQ into PHS
.
.
.
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Chip Gracey
Parallax, Inc.
16.9ns pulses (for the 45% case). That to me is uncomfortably close to 12.5ns; I'd be scared
you'll miss a low or a high pulse depending on how your rise and fall times look. I mean,
this is an asynchronous input, right?
Paul, can you explain the 20MHz remark? If I feed a pin with a 40MHz square wave, I will
get 0->1 sequences at 40MHz, right? Of course the low bit of PHSx will describe a 20MHz
signal; maybe that's what you meant, but certainly the accumulator is accumulating at
40MHz?
I wondered what would happen when the input frequency is greater than clkfreq/2. It will miss pulses, and when the input frequency is exactly equal to clkfreq it will never increment in POSEDGE or NEGEDGE modes, because the samples will always be either 1 or always 0. But if the input is a little less than clkfreq, it will occasionally catch the input in the opposite state and the counter will increment. It seems that the rate of counting in that regime would be (clkfreq - inputFrequency), wheras for the normal usage when (inputFrequency<clkfreq/2), the rate of counting is simply equal to inputFrequency. I'm just pointing out that for some purposes useful information might be had even when it is known that the input frequency is greater than clkfreq/2. This is speculation and would depend on how the state is sampled. Also consider POSDET mode. If the input frequency is exactly equal to clkfreq, then the rate of counting, the proportion of time high, would be determined by the phase of the signals and a "beat" count rate would be formed when the two signals were not equal. That might be useful for some application where an 80mhz wave is launched down a transmission line and the return phase needs to be detected. Or for phase locking.
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Tracy Allen
www.emesystems.com
It's clear there's no formal "synchronizer" on the Prop inputs (if there were, the inputs would be delayed by at least two clock ticks).
It seems me that counts of less, never more than 40 MHz.
Because it cannot "see" more than there.
Because the input is asynchronous, it is sometimes and with certainty going happen that input transitions violate the setup and hold times of the latches. Then there is danger that the state of the latch will be left hanging at some unresolved intermediate value or that it will go into oscillation. This is more likely to happen when the frequencies are high and the setup and hold times are a significant part of the cycle. I don't think we have data on the setup and hold times for the Propeller in general or for the counters in particular., but it must be in the low low nanosecond range. Metastbility is also dependent on the process technology, but I from what I have read, it can never be completely eliminated.
It is the "consequences" of metastabilty that really matter. It can happen and have no consequence whatsoever, or minor consequences like one missed or one extra count. It is more likely to have serious consequences in a complex system where the clocked state has to fan out to perform parallel functions that must all be correct, and lacking that one gate hanging in a metastable state can send the whole system off to la la land. Say, reading an incorrect op-code from a memory because one of the address lines is hanging in the wrong state.
Here is a URL that describes how to generate metastable states on purpose for testing and edification: www.sigcon.com/Pubs/news/4_4.htm. Any scheme like the one I suggested for measuring phase of a high frequency clock signal would push the envelope for metastabilty. But I bet that it is not going to be a worry for most Prop applications.
How about for the case of an asychronous input at clkfreq/3? I don't know. How critical is it that every single event be correctly counted? If it is very critical, then it will be important to test it and get an estimate of the MTBF. That number may so long as to be a non-issue. Maybe not? I wouldn't assume either way if it's really important.
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Tracy Allen
www.emesystems.com
Post Edited (Tracy Allen) : 2/15/2007 9:34:49 PM GMT
The Propeller does not have any·forked circuitry which can land the chip or any of its subsystems into any 'illegal' state based on ambiguity of a pin input.
There is always a high likelihood when inputting a high frequency signal·that what could be termed a 'setup time violation' might occur. No big deal. It gets resolved to '0' or '1' in the first flipflop that it hits. The likelihood of a flipflop being stuck in the·infinitely-small region between '0' and '1' for 12.5ns, or even 1ns, is extremely low. Imagine a penny being dropped onto a vertical razor's edge. Even it landed flat and center, it wouldn't remain long. You might as well also imagine the razor edge vibrating randomly with system noise. And there's no chance of oscillations, either; the two looped inverters at the center of the flipflop·are going to shoot one way or·the other·without·much hesitation, as they form a positive feedback loop.
The ultimate example of forced·metastability·might be·the Propeller's sigma-delta ADC function that can be realized through the CTRs. The whole point is to keep the input pin hovering right at·the threshold. This·would·be very likely·to trigger a metastability wipeout if one was possible, but it doesn't.
When the SX chips were being designed, the head engineer Cheuk Wing Cheng·thought that it would be a·safe move to add a 'SYNC' bit to the·configuration fuses which could select an alternate two-flipflop delay for all pin inputs. The intent, of course,·was to eradicate any potential metastability problems with the inputs. This was a valid concern, because he was using a logic synthesizer to·generate the chip's logic, and he had little control of how the·synthesizer might realize his design.·The synthesizer·could easily have created forked paths, and maybe it even did. At least in the case of the SX, nobody uses the SYNC bit. The reason is this:·experience has shown it's unnecessary, and nobody wants a two-clock delay messing up things like back-to-back·read-modify-write instructions on I/O registers.
The only time I've ever found it was necessary to run inputs through flipflops was when doing FPGA work. This makes sense, since I had no control over how the signal paths were realized. FPGAs really like all their internal nodes to be registered and stable throughout the clock period.
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Chip Gracey
Parallax, Inc.
Now the fundamental frequency will be about 1/2.96 of the 3rd overtone frequency. And that ratio will change every so slightly as the temperature varies.
So I will make a copy of "cnt", then wait for a certain number of the fundamental cycles (maybe 1 million). Then remember what "cnt" is now.
The difference between the two values will indicate the temperature of the xtal.
How another counter is used as a frequency generator to create the output frequency. This will be adjusted according to the temperature as the frequency changes.
Bean.
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"USA Today has come out with a new survey - apparently, three out of every four people make up 75% of the population." - David Letterman
Here is one way I might look at the problem. Suppose the same high frequency, clkfreq/3, asynchronous input goes "simultaneously" into two or several of the counter modules simultaneously. In quotes because of sub-nanoseconds. If the system is completely deterministic, you would expect all of the counters to always show exactly the same count. But due to the uncertainties in the window of setup/hold, there will be times when all of the counters do not agree on how many input pulses have occurred. The difference would be stochastic, but maybe one counter gets one count ahead this time and then one count behind the next, so the differences would average out and no one counter drifts far from the others. On the other hand, it is possible there are systematic biases in the hardware and statistics. It is testable. One count in 80 million? more? less?
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Tracy Allen
www.emesystems.com
If you did a test using clkfreq/3 for 80 million chip clocks, any differences in final counts would be related only to the uncertainties of the·first and last samples, not the ~80 million·in between.
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Chip Gracey
Parallax, Inc.
Post Edited (Chip Gracey (Parallax)) : 2/16/2007 12:54:31 AM GMT
Is an MXCO the same as a TXCO? I don't understand the setup and what is a reference for what. Can there be both a fundamental and also a 3rd harmonic output from the oscillator at the same time?
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Tracy Allen
www.emesystems.com
The MCXO uses a "dual mode oscillator" circuit. So the same crystal is connected to a fundamental and a 3rd overtone circuit at the same time. What this allows you to do is to determine the temperature of the xtal by using the difference between these two outputs.
The 3rd overtone frequency is not quite 3 time the fundamental (about 2.96) and that ratio changes linearly with temperature. It acts like the 3rd ot is at a slightly different xtal angle.
One of the frequencies is fed into a DDS to generate an output frequency. The DDS values are changed as a difference in temperature is detected to keep the DDS output stable.
The advantages are that the temperature is measured directly by the xtal, not by another device that may not be "seeing" the same temperature. Also you can use a very "stiff" (low c1) crystal because you are not using a varactor to adjust the frequency.
Bean.
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"USA Today has come out with a new survey - apparently, three out of every four people make up 75% of the population." - David Letterman
I've been interested in the "digiquartz" barometers and pressure sensors from Paroscientific. Unparalleled accuracy and long term stability. They use a crytal compensated sensor element, but I think there is a separate tuning fork resonator mounted on the same frame as the pressure sensor crystal.
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Tracy Allen
www.emesystems.com
Yes the propeller will be clocked by the F3 frequency which is 20MHz. The F1 frequency will be about 6.6667MHz.
Here is a graph of some data we took some time ago. The Blue and Red lines are the F1 and F3 frequency, and go with the scale on the left. The yellow line is the temperature count and goes with the scale on the right.
The temperature count is a count of the F3 frequency for a period of 16777220 F1 cycles (about 2.5 seconds). The count is then normalized (offset) so that -55°C gives 0.
BTW this oscillator met·±0.1ppM from -55°C to +95°C
Bean.
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"USA Today has come out with a new survey - apparently, three out of every four people make up 75% of the population." - David Letterman
Post Edited (Bean (Hitt Consulting)) : 2/16/2007 7:29:55 PM GMT
Thanks,
Frank
>When clocking the propeller at 80MHz, what is the maximum frequency that can be counted using the POSEDGE mode ?
>I read the counter app note, but it doesn't say. I assume it is some division of the propeller clock.
> Bean.
http://www.parallax.com/dl/appnt/prop/AN001-PropellerCounters-v1.0.zip
RoboGeek
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·
Either I found a bug in the frequencyCount.spin file, or I don't understand.
PUB Go | freq
txt.start(16)
cognew(@entry, freq) ' should be CHANGED TO cognew(@entry, @freq)
repeat
txt.out($00) 'clear the screen
txt.dec(freq) 'display the value (in Hz)
...
DAT
...
wrlong new, par