bit alignment code - LONG
Anyone bored enough to look over some code?
I have a stream of bits that arrive from a floppy disk drive and my ISR captures the data. This works fine. I've just added a 24-bit buffer and I'm attempting to byte-sync my datastream to a SYNC value "0x4489." SYNC value does not show up in regular data. I'm attempting this as the data is arriving on the fly. The idea is that unaligned data will simply be written to my external SRAM through the back end of the buffer until a SYNC value shows up. Once that happens, I will adjust the position of the SYNC(and subsequent data) in the buffer by skipping bit writes to the SRAM until I'm properly aligned. Note that while this skipping/aligning is going on, I'm still making regular shifts of data into the buffer.
All writes to the buffer and SRAM are single bit writes. There are no timing/clock/interrupt issues here. Assume one bit arrives via WKPND_B every 2us roughly. Either an edge happened, or RTCC rollover occurred. This is my data.
Am I close or on the right track here?
Thanks
Keith
I have a stream of bits that arrive from a floppy disk drive and my ISR captures the data. This works fine. I've just added a 24-bit buffer and I'm attempting to byte-sync my datastream to a SYNC value "0x4489." SYNC value does not show up in regular data. I'm attempting this as the data is arriving on the fly. The idea is that unaligned data will simply be written to my external SRAM through the back end of the buffer until a SYNC value shows up. Once that happens, I will adjust the position of the SYNC(and subsequent data) in the buffer by skipping bit writes to the SRAM until I'm properly aligned. Note that while this skipping/aligning is going on, I'm still making regular shifts of data into the buffer.
All writes to the buffer and SRAM are single bit writes. There are no timing/clock/interrupt issues here. Assume one bit arrives via WKPND_B every 2us roughly. Either an edge happened, or RTCC rollover occurred. This is my data.
Am I close or on the right track here?
' -------------------------------------------------------------------------
INTERRUPT NOCODE
' -------------------------------------------------------------------------
ASM
SETB rb.1 'debug pin(inside interrupt)
CLR RTCC
CLR FSR
ISR_Start:
MODE $09
MOV !RB,#%00000000
'W NOW CONTAINS A %00000001 IF FIRED BY EDGE, 0 IF RTCC
mov myres, w
'myres.0 has the actual bit value
MOVB C, MYRES.0 'Put myres.0 into C to be shifted in
'shift the bit into the 24-bit buffer
RL BYTE1
RL BYTE2
RL BYTE3
MOVB MYRES.0, C 'this is the output bit if we need to write it
CJNE BYTE2, #$44, notasync
CJNE BYTE1, #$89, notasync
CJE bitcounter, #1, notasync 'this is a sync but its already aligned right
'we've seen an unaligned sync
'the number of bits we need to skip = the number of bits we are currently out of alignment
'so let's subtract the number of bits we've written for the current byte from 8
'and then skip that number of bits
MOV skipwrite, #8
SUB skipwrite, bitcounter
notasync:
CJE SKIPWRITE, #0, skipdaskip 'if we are not in the process of realigning
dec skipwrite
CJA SKIPWRITE, #0, goback
'skipwrite just went from 1->0, last bit to skip, let's reset bitcounter to 8
'we are now properly aligned.
MOV bitcounter, #8
jmp goback
skipdaskip:
dec bitcounter
CJA BITCOUNTER,#0, skipbcreset 'snz wont work because mov is multi-byte instruction
mov bitcounter, #8 'reset bitcounter
skipbcreset:
CLRB SCK 'make sure clock is low to start with
NOP
MOVB SI, myres.0 'send bit to fram
NOP 'satisfy 5ns data setup time
SETB SCK 'raise clock notifying chip to read the data
'COUNT THE Bit stored
IJNZ lobyte, goback
IJNZ hibyte, goback
inc superhibyte
goback:
CLRB rb.1
MOV W, #-100
retiw
ENDASM
Thanks
Keith
