I wonder what a Propeller chip could do if it was built with 0.65 nanometer tech? But really the biggest problem I see for a chip like this isn't software, its main memory. A chip like Intel's 80-core test chip could easily saturate main memory 100 times faster than what a current PC uses. The Propeller sidesteps this by using only internal memory. At the moment using only internal memory doesn't work for applications with multi-gigabyte data sets. (FEA codes are a good example. worst case the memory requirements go up with the square of the number of nodes in the mesh. Even now solution speeds are limited by main memory on modern single core CPUs)
It would get really hot!, the Intell chip you are comparing the prop to, uses the amount of electricity of a 60 watt light bulb. Imagine the battery life on a laptop!. It will HAVE to have fans (moving parts) the premice of solid state microcontrolled products is their ability to just work, for a very long time, NASA still uses the 8086. That 80 core, would never go into space for a long journey, or be a block box ethernet to serial converter, or any other mundane helper, microcontrollers will.
Quite true. The Intel beast is no microcontroller/microprocessor. More a supercomputer, compare at 6000 watts, still a trend toward small and green.
It is actually the process using the hafnium oxides and silicates for the gate insulator that caught my attention in relation to lower power, as promised by Intel, or a similar development by IBM. Hafnium dioxide has a dielectric constant 6 times that of silicon dioxide. That means it takes less charge to control the gate current, and also allows a thicker layer, to minimize leakage. I general it would allow cooler operation, and decreased cost and size along the amazing progression of Moore's law.
In theory it could be something for the next generation Prop as it migrates to a smaller geometry, in order to avoid higher quiescent currents in so far as they are due to gate leakage. But I guess (completely as an outsider) it will be a long time before those technologies move past the proprietary stage and make it to other foundaries. I understand the hafnium oxide gate also requires a certain proprietary metal connection, and will not be compatible with polysilicon. They are keeping a tight IP control over the nature of that metal, whereas a lot of the research on the hafnium compounds seems to be available in the open literature.
"Any intelligent fool can make things bigger, more complex, and more violent. It takes a touch of genius -- and a lot of courage -- to move in the opposite direction."
Albert Einstein
The current Propeller is made in a 0.35um process, which is a pure 3.3V process. The next version is being built in a 0.18um process, which·uses 1.8V for core and 3.3V for I/O. The smaller the transistor gate length (which defines the process 'size'), the lower the operating voltage. The lower the operating voltage, the lower the threshold has to be set for the transistors to have a good ratio of ON to OFF current. The lower the threshold gets, the more the transistors leak, because you can't pinch them off with Vgs=0. They are always ON to some degree. Going back to a .5um/5V process, when Vgs=0 the transistor is extremely OFF.
The trouble with going smaller and smaller is that the leakage current increases exponentially. I calculated that 0.18um leaks 80 times as much as 0.35um, and 90nm leaks 400 times as much as 0.18um. I heard in a chip seminar a few years ago that it was anticipated that 65nm processes would leak so much that it would account for 70% of a chip's power dissipation. Imagine that; no clock and yet it's burning up. This is how modern graphics cards are becoming. Some dissipate 160W and have integrated cooling systems.
I think that 0.35um is really the last stop where you have practically no leakage. The current Propeller leaks·600na. The next·Propeller, considering its increase in complexity, and that it will be in a 0.18um process,·will probably leak 100uA continuously.
Chip,
What's the prospect (in general, not the Prop-2 specifically) for power switching portions of a chip to prevent this magnitude of leakage when sections of a chip are not needed? I'm imagining having a power supervisor done in 3.3V with only a few gates (that can leak) that switches power to 1.8V sections of the chip. This would be for a WAITCNT or WAITPxx like instruction, but the processor would set up the power supervisor and then shut itself off completely. I'm imagining that it would be relatively slow to power up the processor, but this would enable you to have an extremely low power mode (despite this magnitude of leakage) with some restart speed penalty for those situations where you're running off a small battery. Very nicely, the current Propeller can do this without the power switching.
Mike
Mike Green said...
Chip,
What's the prospect (in general, not the Prop-2 specifically) for power switching portions of a chip to prevent this magnitude of leakage when sections of a chip are not needed? I'm imagining having a power supervisor done in 3.3V with only a few gates (that can leak) that switches power to 1.8V sections of the chip. This would be for a WAITCNT or WAITPxx like instruction, but the processor would set up the power supervisor and then shut itself off completely. I'm imagining that it would be relatively slow to power up the processor, but this would enable you to have an extremely low power mode (despite this magnitude of leakage) with some restart speed penalty for those situations where you're running off a small battery. Very nicely, the current Propeller can do this without the power switching.
Mike
The biggest leakage, by far,·occurs in the SRAM arrays, since there·is the equivalent of two inverters for each bit of storage. With even 128KB of main SRAM, thats 2M inverters. I suppose their supply voltage could be lowered, but not completely, lest they lose their contents. I really haven't looked into doing this yet, but perhaps we'll make some efforts here. Thanks for pointing this out.
Thanks for the explaniation of the leakage issue. Might it be possible to apply a small negative bias to the gates in the core in order to cut them off more fully? Not necessarily by adding another power supply, but by somehow using the 3.3 volt i/o power supply in a manner to bias the SRAM array up by a couple of tenths of a volt so that the control lines can effectively go negative for those transistors?
this is an interesting discussion. hope its ok if I join in.
first of all I would truly like to thank parallax and there efforts with the propeller. the more I study it the more im impressed, with what you had to work with. well done.
I happen to agree with the idea that it would be better to be able to interface with a chip rather than "login" to it. I believe the future is monitoring data. im sure there is a small market that it "would be a nice to have" to have an IDE built in. but.. being able to interface with data serves both purpouses. weather thats done through a t-base 10 or usb or seriel.. I believe the future is better served persuing that effort.
I happen to be a IC layout Designer. the first major project I worked on was the p55c if any of you remember that. i have worked on .35um all the way down to .045um or 45 nanometer. something i am seeing more and more of now is keeping the substright and well ties on a seperate bus. for analog as well as digital. its a lot of work. but now you can bias the substright.
dont know if I have a comment about linux vs MS. I use both all the time. i understand that progress makes people mad. but if we didnt have progress, we would still be using 286's and windows 1.0. I dont like MS anymore then you. its just an evil I have learned to live with.
You said...
...I happen to be a IC layout Designer. the first major project I worked on was the p55c...
I was right across the street from you when I worked for National Semiconductor.· Most of the work that I have done has been in the high speed communication division which involved
the Gig Mac Phy 10/100/1000 Ethernet chipsets.· The processes that I have worked on range from 0.35um to 0.11um (110nm) and I have also seen what you describe by keeping the substrate
and well ties on a separate bus (Usually just the BULK (P-Tap) connection).· In the 0.18um process we are currently using, VSS is tied to BULK.· VDD is tied to N-Well, there are no "HOT" wells.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ Beau Schwabe
IC Layout Engineer
Parallax, Inc.
Post Edited (Beau Schwabe (Parallax)) : 2/14/2007 12:33:50 AM GMT
right thats the normal way to do it. but bulk is like a spunge right, so you can tweek the vt's a little by keeping them seperate.. or so the thinking go's, I dont know if I buy it.
I worked on the P2 the P3 then I went and worked for cyrix for a while. then went and did a bunch of other stuff in canada and england. then.. I went and worked on the prescott, and a year later cedarmill projects. so I have got to do a whole range of things. cmos, bicmos, RF and just plain bipolor.
now im working for an R&D company on ladar chips that will be used to change the way robots see. exciting work. so we shoot off a laser or scan with a it, and mesure the photons that come back.
You said...
...right thats the normal way to do it...· ...you can tweek the vt's a little by keeping them seperate...· ...I dont know if I buy it...
Thing is, I have seen it done both ways for the same process (different chip)...· Most often, this practice was done
when there was mixed signal custom layout. (Analog and Digital)
You said...
...now im working for an R&D company on ladar chips that will be used to change the way robots see...
Interesting approach!· I put together the High Speed ADC used·by Fovian·X3.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ Beau Schwabe
IC Layout Engineer
Parallax, Inc.
right now, our adc's are off chip. I really dont know if we will plan to make our own on chip adc's? its kind of a 6 in one hand and a half dozen in the other.. light is really really fast[noparse];)[/noparse] so we get our return signal... at the speed of light. that gives us all day to read off the data. we can read off the data at 40MHz and still have all day before the next sample. we have several different types of chips in R&D. some are what we are calling hi spped and some that are just 32x1 "detector" that have 15 samples each.. sounds like a lot but at the speed of light it takes 15ns to gather all that data. ok... im done now. I will shup up[noparse];)[/noparse]
really tho, you did a great job on the propeller. i just got mine and am trying to warp my head around spin. not that its to hard but its time you know? I have so many balls in the air its hard to find the time. this chip has enough power to do some real work tho and thats what is so cool about it. I outgrew my BS2 really quickly not that its a bad chip but its just not powerful enough to do some of the things I want to do.
what tools did you use? did parallax pony up for cadence? and how many layout people did you have? what was your workload like?
The ADC was designed to run 12-bit resolution at 80MHz sample rate.
You said...
...really tho, you did a great job on the propeller...
Thanks, but I can't take credit for the layout of the·350nm Propeller.· Another guy no longer at Parallax named Frank Olson deserves the layout credit.
The tools we are using for layout in the 180nm process are from a company called Silicon Canvas.· I can say that after·5 years of using Cadence, that
"Laker" (Silicon Canvas's layout editor) is almost identical ... look , feel, taste, etc. to Cadence's Virtuoso Layout Editor.· Even some of the "buggy"
keystroke quirks are the same as far as how they respond/react.· Currently we have one IC-layout guy.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ Beau Schwabe
IC Layout Engineer
Parallax, Inc.
Comments
My 2¢
Marty
It is actually the process using the hafnium oxides and silicates for the gate insulator that caught my attention in relation to lower power, as promised by Intel, or a similar development by IBM. Hafnium dioxide has a dielectric constant 6 times that of silicon dioxide. That means it takes less charge to control the gate current, and also allows a thicker layer, to minimize leakage. I general it would allow cooler operation, and decreased cost and size along the amazing progression of Moore's law.
In theory it could be something for the next generation Prop as it migrates to a smaller geometry, in order to avoid higher quiescent currents in so far as they are due to gate leakage. But I guess (completely as an outsider) it will be a long time before those technologies move past the proprietary stage and make it to other foundaries. I understand the hafnium oxide gate also requires a certain proprietary metal connection, and will not be compatible with polysilicon. They are keeping a tight IP control over the nature of that metal, whereas a lot of the research on the hafnium compounds seems to be available in the open literature.
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Tracy Allen
www.emesystems.com
Albert Einstein
found this:
http://forums.parallax.com/showthread.php?p=593738
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Tracy Allen
www.emesystems.com
The trouble with going smaller and smaller is that the leakage current increases exponentially. I calculated that 0.18um leaks 80 times as much as 0.35um, and 90nm leaks 400 times as much as 0.18um. I heard in a chip seminar a few years ago that it was anticipated that 65nm processes would leak so much that it would account for 70% of a chip's power dissipation. Imagine that; no clock and yet it's burning up. This is how modern graphics cards are becoming. Some dissipate 160W and have integrated cooling systems.
I think that 0.35um is really the last stop where you have practically no leakage. The current Propeller leaks·600na. The next·Propeller, considering its increase in complexity, and that it will be in a 0.18um process,·will probably leak 100uA continuously.
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Chip Gracey
Parallax, Inc.
What's the prospect (in general, not the Prop-2 specifically) for power switching portions of a chip to prevent this magnitude of leakage when sections of a chip are not needed? I'm imagining having a power supervisor done in 3.3V with only a few gates (that can leak) that switches power to 1.8V sections of the chip. This would be for a WAITCNT or WAITPxx like instruction, but the processor would set up the power supervisor and then shut itself off completely. I'm imagining that it would be relatively slow to power up the processor, but this would enable you to have an extremely low power mode (despite this magnitude of leakage) with some restart speed penalty for those situations where you're running off a small battery. Very nicely, the current Propeller can do this without the power switching.
Mike
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Chip Gracey
Parallax, Inc.
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Tracy Allen
www.emesystems.com
this is an interesting discussion. hope its ok if I join in.
first of all I would truly like to thank parallax and there efforts with the propeller. the more I study it the more im impressed, with what you had to work with. well done.
I happen to agree with the idea that it would be better to be able to interface with a chip rather than "login" to it. I believe the future is monitoring data. im sure there is a small market that it "would be a nice to have" to have an IDE built in. but.. being able to interface with data serves both purpouses. weather thats done through a t-base 10 or usb or seriel.. I believe the future is better served persuing that effort.
I happen to be a IC layout Designer. the first major project I worked on was the p55c if any of you remember that. i have worked on .35um all the way down to .045um or 45 nanometer. something i am seeing more and more of now is keeping the substright and well ties on a seperate bus. for analog as well as digital. its a lot of work. but now you can bias the substright.
dont know if I have a comment about linux vs MS. I use both all the time. i understand that progress makes people mad. but if we didnt have progress, we would still be using 286's and windows 1.0. I dont like MS anymore then you. its just an evil I have learned to live with.
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Muahdib
IC layout designer
Austin Texas
the Gig Mac Phy 10/100/1000 Ethernet chipsets.· The processes that I have worked on range from 0.35um to 0.11um (110nm) and I have also seen what you describe by keeping the substrate
and well ties on a separate bus (Usually just the BULK (P-Tap) connection).· In the 0.18um process we are currently using, VSS is tied to BULK.· VDD is tied to N-Well, there are no "HOT" wells.
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Beau Schwabe
IC Layout Engineer
Parallax, Inc.
Post Edited (Beau Schwabe (Parallax)) : 2/14/2007 12:33:50 AM GMT
I worked on the P2 the P3 then I went and worked for cyrix for a while. then went and did a bunch of other stuff in canada and england. then.. I went and worked on the prescott, and a year later cedarmill projects. so I have got to do a whole range of things. cmos, bicmos, RF and just plain bipolor.
now im working for an R&D company on ladar chips that will be used to change the way robots see. exciting work. so we shoot off a laser or scan with a it, and mesure the photons that come back.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Muahdib
IC layout designer
Austin Texas
Thing is, I have seen it done both ways for the same process (different chip)...· Most often, this practice was done
when there was mixed signal custom layout. (Analog and Digital)
Interesting approach!· I put together the High Speed ADC used·by Fovian·X3.
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Beau Schwabe
IC Layout Engineer
Parallax, Inc.
right now, our adc's are off chip. I really dont know if we will plan to make our own on chip adc's? its kind of a 6 in one hand and a half dozen in the other.. light is really really fast[noparse];)[/noparse] so we get our return signal... at the speed of light. that gives us all day to read off the data. we can read off the data at 40MHz and still have all day before the next sample. we have several different types of chips in R&D. some are what we are calling hi spped and some that are just 32x1 "detector" that have 15 samples each.. sounds like a lot but at the speed of light it takes 15ns to gather all that data. ok... im done now. I will shup up[noparse];)[/noparse]
really tho, you did a great job on the propeller. i just got mine and am trying to warp my head around spin. not that its to hard but its time you know? I have so many balls in the air its hard to find the time. this chip has enough power to do some real work tho and thats what is so cool about it. I outgrew my BS2 really quickly not that its a bad chip but its just not powerful enough to do some of the things I want to do.
what tools did you use? did parallax pony up for cadence? and how many layout people did you have? what was your workload like?
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Muahdib
IC layout designer
Austin Texas
Post Edited (Rontopia) : 2/14/2007 4:20:00 PM GMT
The ADC was designed to run 12-bit resolution at 80MHz sample rate.
Thanks, but I can't take credit for the layout of the·350nm Propeller.· Another guy no longer at Parallax named Frank Olson deserves the layout credit.
The tools we are using for layout in the 180nm process are from a company called Silicon Canvas.· I can say that after·5 years of using Cadence, that
"Laker" (Silicon Canvas's layout editor) is almost identical ... look , feel, taste, etc. to Cadence's Virtuoso Layout Editor.· Even some of the "buggy"
keystroke quirks are the same as far as how they respond/react.· Currently we have one IC-layout guy.
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Beau Schwabe
IC Layout Engineer
Parallax, Inc.
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Muahdib
IC layout designer
Austin Texas