··············································Wafer-Level Packaging (WLP)refers to the technology of packaging an integrated circuit at wafer level, instead of the traditional process of assembling the package of each individual unit after wafer dicing.· WLP is essentially a true chip-scale packaging (CSP) technologies .This is a single-die, direct surface mountable package with an area of no more than 1.2 X the original die area.· The acronym 'CSP' used to stand for 'Chip Size Package,' but very few packages are in fact the size of the chip. · ·····················································WL-CSP is a low profile, true chip size package that is entirely built on a wafer using front-end and back end processing. The wafers can be batch-processed in a fab, which reduces the number of materials and packaging steps, reduces inventory, and allows for wafer level burn in and test. This technology is driven by cost, size, and ease of testing and is ideal for low to mid I/O devices. Peripheral bond pads fromthe die are redistributed into an area array using a photo dielectric and a redistribution metal, eliminating the need for a substrate or interposer. Solder balls are placed on to the redistributed metal bond pads and reflowed, creating a large standoff which improves reliability. The bump structure and pad geometry of the test vehicle was optimized using Simulation and validated by experimentation. This WL-CSP technology was evaluated using a 5 x 5 mm2 die with a 0.5mm pitch 8 x 8 arrays of solder bumps level interconnects. Package and board level reliability results for this WL-CSP structure have been reported previously · · · ····························
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··········································· ··········WL-CSP is a low profile, true chip size package that is entirely built on a wafer using front-end and back end processing. The wafers can be batch-processed in a fab, which reduces the number of materials and packaging steps, reduces inventory, and allows for wafer level burn in and test. This technology is driven by cost, size, and ease of testing and is ideal for low to mid I/O devices. Peripheral bond pads fromthe die are redistributed into an area array using a photo dielectric and a redistribution metal, eliminating the need for a substrate or interposer. Solder balls are placed on to the redistributed metal bond pads and reflowed, creating a large standoff which improves reliability. The bump structure and pad geometry of the test vehicle was optimized using Simulation and validated by experimentation. This WL-CSP technology was evaluated using a 5 x 5 mm2 die with a 0.5mm pitch 8 x 8 arrays of solder bumps level interconnects. Package and board level reliability results for this WL-CSP structure have been reported previously
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