counter jitter

Graham Stabler

is it possible to calculate the likely jitter in the nco modes?

I'm sure I have read this but can't find it.

Graham

kuisma

The jitter will be randomly distributed in the half-open interval [noparse][[/noparse]0..1/SystemClock[noparse][[/noparse]
i.e. [noparse][[/noparse]0..12.5nS[noparse][[/noparse] at 80MHz.

- Mikael

Graham Stabler

If the worse case phase jitter is only 12.5ns then I'm cooking on gas.

cue the evil laugh

Graham

kuisma

PHSA is incremented with FRQA each clock cycle. To get no jitter, it is required that PHSA is exactly 2^31 at an incrementation. This will only occur with FRQA equal to 2^N. Else PHSA can go from for example 2^31-5 to 2^31+5 at an incrementation, toggling bit 31 little too late (5/10 of a system clock period), but never more late then the length of the system clock period. This is no problem generating low frequencies, but can be devastating if you are trying to generate a 30MHz signal.

- Mikael

Graham Stabler

Luckily my stepper motors do not appreciate 30Mhz step frequencies [noparse]:)[/noparse]

Graham

Tracy Allen

Jitter came up in this thread "high frequency distortion":

http://forums.parallax.com/showthread.php?p=583301

Jitter would be insignificant for most intents and purposes, when the PHSx period is much much greater than 12.5nS (80mhz clkfreq). For example, to generte a 999 hertz output, with FRQA=53633, the output consists of a mixture of periods of length 80080 * 12.5 nS and 80081 * 12.5nS. That tiny difference is probably not going to matter, unless the intent is in fact to make a super accurate 999 Hz oscillator. Those periods correspond to a mixture of two frequencies, 999.001 Hz and 988.989 Hz. The the mixture of the two periods follows exact numerical rules and the phase slips occur in an entirely predictable pattern.





The slip in phase is always in plus or minus a 12.5 nS subharmonic content is closely tied to the exact ratios.

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Tracy Allen
www.emesystems.com