CTRMODE, FRQx and PHSx
Jim C
Posts: 76
The time has come to learn about frequency generation along with detecting and counting edges. There have been a few threads about this but none recently, and I am looking for a thread from a few months ago.
The thread included a chart or worksheet about what each CTRMODE did, in sort of a spreadsheet format. It explained how all the NCO and PLL business of the counters worked. I've searched the forums every way I can think of, to no avail.
Does anyone remember this thread?
Thanks,
Jim C
The thread included a chart or worksheet about what each CTRMODE did, in sort of a spreadsheet format. It explained how all the NCO and PLL business of the counters worked. I've searched the forums every way I can think of, to no avail.
Does anyone remember this thread?
Thanks,
Jim C
Comments
http://forums.parallax.com/forums/default.aspx?f=25&m=143440&g=143487#m143487
I need to get back to this though there was talk of Parallax doing more documentation.
Graham
Yes, that's the thread I was looking for. Thank you very much.
I see you have put alot of work into this, and maybe clarify a couple things. In your little write-up, you state:
"So if we consider (CTRMODE) mode 00010 we find that the value we place in FRQx is accumulated into PHSx on every clock cycle. The MSB of PHSx which acts as an NCO is fed into the X16 PLL and the multiplied signal (subject to the PLL tap selected) applied to APIN as defined in CTRA."
This was helpful for me, as this statement is sort of missing from the manual. It was not clear to me that there is any accumulation going on in the PLL modes. I'm still alittle fuzzy, though, on the connection between FRQx and the output frequency. It seems to relate to 2**28, in that if FRQx is set to that, the output frequency is 80 MHz.
There is also the code from the Synth.spin object, which computes the FRQx for a given output frequency, but I don't quite understand the logic there.
Any insight would be appreciated.
Thanks,
Jim C
Graham
So you are interested in mode 2 (00010)? I can give you a synopsis of the mode.
·
Mode 2 is identical to Mode 4 (NCO/PWM) with the addition of the PLL multiplier at the end. So I’ll start off by explaining mode 4.
·
The highest bit of PHS is the output to APIN, each and every system clock FRQ is added to PHS and PHS[noparse][[/noparse]31] is output the APIN. So if FRQ contains $8000_0000; PHS will be $0000_0000, $8000_0000, $0000_0000, … and APIN will be 0,1,0,… or half the system clock. Likewise if FRQ was $4000_0000, APIN would be 0,0,1,1,0,0,… or a quarter the system clock. The output frequency of this mode is FRQ/232 x System clock for FRQ <= $8000_0000. For values greater than $8000_0000, the out put frequency will decrease in mirror fashion ( 232 – X = X), due to the Nyquist theorem (to express a frequency X requires a sample frequency of 2X or greater). For values of FRQ not a power of 2 (FRQ <> 2N), there will be jitter present on the frequency output on the APIN. This is because an equal amount of 1’s to 0’s are not being produced.
·
Mode 2 has all the properties of Mode 4 as described above but has a PLL. This PLL is always multiplying the bit pattern in PHS[noparse][[/noparse]31] by 16x the frequency. You may choose 1 of 8 different taps of the PLL as your output to APIN. In order they are VCO/128, VCO/64, VCO/32, VCO/16, VCO/8, VCO/4, VCO/2, VCO/1, where VCO is the 16x PLL output. So, in terms of the frequency established by PHS[noparse][[/noparse]31], these are the outputs available by the PLL: 1/8, 1/4, 1/2, 1, 2, 4, 8, 16 times the PHS[noparse][[/noparse]31] bit pattern. The PLL has a range of frequencies the input pattern must be between in order to operate, and the PLL in the counter expects an input frequency of 4 to 8MHz. This results in a 16x output of the PLL in 64 to 128 MHz range, but given the 8 taps provided, a range of 500kHz to 128MHz are possible for the freqency produced on APIN·
·
You may wonder why output frequencies 1/8, 1/4, 1/2, and 1 of the PLL are provided when these frequencies are obtainable via Mode 4. This is to help de-jitter the signal when the FRQ is not equal to 2N. The PLL can completely de-jitter a FRQ of 2N+2N-1 (two adjacent 1’s in the binary value of FRQ) and does a good job at de-jittering a FRQ value where the spread of the 1’s in the binary value are 3 positions. However any spreads greater than this the PLL is not capable of de-jittering, some amount of de-jittering will be done, but not enough.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Paul Baker
Propeller Applications Engineer
Parallax, Inc.
Post Edited (Paul Baker (Parallax)) : 10/7/2006 7:23:24 PM GMT
Hi Jim,
I'll tackle explaining the background and deriviation.
The PHSx register is aptly called a phase accumulator. Phase for any periodic waveform varies over one cycle, and you can think of phase from zero to one in the abstract, or 0 to 100%, or zero to 2 pi radians, or 0 to 360 degrees, or in the propeller counters as 0 to 2^32 = 4294967296. It is all just a matter of scale, but the propeller counter gives lots and lots of phase resolution. Phase of 180 degrees on the cycle is phsa = 2^31, and that is the point below which the msb=0 and above which msb=1. It is easy to tranlate phase to the PHSx phase accumulator. It is simply the "distance" along the phase accumulator from 0 to 4294967296.
Now, FRQx is added to the PHSx on every clock cycle. Look at FRQx as a fraction of the total phase, 2^32. For example, if you want to translate it to degrees from 0 to 360, you would have
degrees = 360 * FRQx / 2^32.
Every time FRQx is added to PHSx, the phase advances that many degrees. It might be a very tiny fraction of a degree (e.g. when FRQx=1) and take a long time to get through the whole accumulator, or it can flip 180 degrees each time. (e.g., when FRQx=2^31), very fast. Pop quiz: what is the value of FRQx that advances the phase one degree each iteration? Answer, FRQx = 1 * 2^32 / 360 = ???.
How long does it take for one cycle? That is, how many time does FRQx have to be added to PHSx before it rolls over and starts over from zero? That is simple. Here:
Add FRQx times N to get up to 2^32. At the halfway point, the msb of PHSx flips from 0 to 1. At the end, when PHSx rolls past $ffffffff, it generates a carry (important in DUTY mode).
So far, clock time has not entered the picture. It is all numbers. How do you connect with CLKFRQ? FRQx is added to PHSx on every clock cycle in the NCO modes. (That includes the DUTY and Logic Always and also the NCO that underlies the PLL mode). The period of the Prop master clock is 1/CLKFREQ. It takes N = 2^32 / FRQx iterations (clock cycles) for the phase to accumulate all the way through one cycle. So the total time for one cycle is:
Now suppose you want a specific output frequency, Fout. The period of that is,
Combine those two equations based on period and you have,
Rearrange to solve for the critical value of FRQx and,
If you need to generate a fixed frequency, you can use a calculator to plug in the numbers and enter the resulting FRQx as a constant or data in your program. On the other hand, if the FRQx value needs to be calculated at run time, then the binary long division program you see in synth.spin is necessary. Here is is without the PLL factors, just to set a frequency for the NCO:
PRI frqVal(a, b, bits) : f ' entry conditions a<b, a<=2^31, b<=2^31 repeat bits 'calculate f: a/b = f/(2^32) a <<= 1 ' multiply a times two f <<= 1 ' multiply b times two if a => b a -= b ' if a>b, then subtract b from a f++ ' and set the least significant bit of fThis is binary long division for the fractional part (as opposed to the integer part). I have more about the BASIC Stamp version at www.emesys.com/BS2math2.htm#binary_long
At each step n in the algorithm, it kicks out the approximation, f/(2^n) ~= a/b. If bits=32 going in, then the result is the number that provides the best approximation to f/(2^32) ~= a/b. When a=Fout, and b=CLKFREQ, then it returns
That is exactly what is needed for FRQx!
Note that this will always satisfy the entry conditions. Both Fout and CLKFREQ are less than 2^31, and Fout of necessity is less than CLKFREQ. This applies to the base NCO. In the PLL modes, the PLL multiplies the NCO output frequency to a value that may be greater than CLKFREQ, but that is a separate process. In Synth.spin, the calculation of the FRQx factor rolls the PLL multiplier/divider into the calculation.
In pasm, the binary approximation algorithm becomes,
'enter with a and b: a < b, a < 2^31, b <= 2^31 ' exit with f: (f / 2^32) best approximation to (a / b) ' if different number of bits, then f: f/(2^n) = a/b ratiox mov t,#32 ' number of bits mov f,#0 ' frequency -- will be result loop shl a,#1 ' double the value of a shl f,#1 ' double the estimate of f, appoximation f/(2^t) =~ a/b cmpsub a, b ' if a>=b then a:=a-b, carry:=1, else a unchanged, carry:=0 addx f,#0 ' add carry to f djnz t,#loop ' do all bits ratiox_ret retThe efficiency of pasm-- it rolls comparison and the subtraction into one instruction, the cmpsub a,b!
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com
Post Edited (Tracy Allen) : 10/7/2006 7:40:07 PM GMT
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Paul Baker
Propeller Applications Engineer
Parallax, Inc.
Right on! It beleive it is always helpful to look at the elephant from many different angles.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com
·
And for those interested in the block diagram for the entire Counter module:
·
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Paul Baker
Propeller Applications Engineer
Parallax, Inc.
Post Edited (Paul Baker (Parallax)) : 10/7/2006 8:14:52 PM GMT
Jim, I should point out one more condition on the algorithm, which is, Fout <= CLKFREQ/2. That is the maximum frequency attainable from the NCO, occurring when FRQa = 2^31. The output frequency increases for values of FRQx from 1 to 2^31. But then it decreases again for values of FRQx above 2^31 and reaches a minimum again at FRQx = $ffffffff, which is -1 in twos complement. That is retrograde phase progression.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Paul Baker
Propeller Applications Engineer
Parallax, Inc.
The one fundemental problem for most people using the counters is understanding the basic accumulation to frequency relationship, although writing out examples for lower bit counts is nice it doesn't really explain things like you have done. Its true understanding that gives you real power over everything.
Paul, It was very interesting to hear about the jitter and when the pll should be used.
Any e.t.a on the docs? What will they consist of? Will it be datasheet style or explanation and examples or a mix?
Graham
This is truly deep and complex. I will have to study all the explanations here for a few days, but in the meantime I'd like to think out loud about this.
I understand the NCO counter, where setting frqa to 2**31 gives a output frequency of 40 MHz. And, it makes sense that the PLL modes are the same, with a 16x multiplier. But I seemed to be 2x off somewhere when trying to get everything to fit.
Using Synth.spin, and computing for an output frequency of 80 MHz, the frqa required is 268,435,456 with a PLL of %111. This was confirmed on the 'scope. And using Excel, I calculate 268,435,456 is 2**28. So, in PLL mode frqa of 2**28 yields 80 MHz, checked three ways. In NCO mode, frqa of 2**31 yields 40 MHz, and frqa of 2**28 yields 5 Mhz. This multiplied by the built-in PLL 16x yields 80 MHz. That's all as it should be.
The problem I had was I started with experiments, by changing this or that parameter and checking the scope. Then tried to figure out the logic. In working backwards like this, I was always 2x off, when trying to predict what was going to happen in the PLL modes.
By starting with the logic, and confirming with experiments, it's all starting to click THe more I look at this, and roll it around, I realize I was starting at the wrong end. If you know ahead of time that PLL mode is the same as (NCO mode x 16), then to get to 80 MHz out you'd need an NCO equivalent of 5 MHz, or 2**28.
By starting with the logic and confirming with experiments instead of the other way around, it's all starting to click.
Thanks y'all for picking up where the manual ended.
Jim C.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Paul Baker
Propeller Applications Engineer
Parallax, Inc.