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Minimum current/voltage to make the pin input as HIGH. — Parallax Forums

Minimum current/voltage to make the pin input as HIGH.

MrNobodyMrNobody Posts: 13
edited 2006-09-07 21:56 in BASIC Stamp
Hi...
I want to attach the output of an LDR circuit into a pin in Pasic Stamp 2 (after making that particular pin an INPUT).
What is the minimum current and voltage required to make the input HIGH. In another words, what is the minimum voltage that I need to output from the LDR circuit to turn the pin on.
Thanks.

Comments

  • Chris SavageChris Savage Parallax Engineering Posts: 14,406
    edited 2006-09-07 14:16
    Hello,

    ·· Your voltage needs to be above 1.4V to register as a HIGH.· Take care.

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    Chris Savage
    Parallax Tech Support
  • allanlane5allanlane5 Posts: 3,815
    edited 2006-09-07 15:03
    Oh, and the input impedance of a BS2 pin is around 10 Megohms, so the input pin will take VERY little current at 1.4 volts.
  • MrNobodyMrNobody Posts: 13
    edited 2006-09-07 21:28
    Thanks..
    Is there a way where I can measure the input impedance..?
    Like which pin should I place my ohmeter? And I only measure it after I set the pin as input and measure it whie it is running rite..?

    If my understanding is right, high impedance and low current is to protect the Basic Stamp rite..? It will not affect the other output pins as the voltage and current is only use to turn the input pin HIGH.

    Post Edited (MrNobody) : 9/7/2006 9:36:49 PM GMT
  • Mike GreenMike Green Posts: 23,101
    edited 2006-09-07 21:56
    Many ohmmeters will not accurately read a resistance/impedance this high. If you look at the datasheet for the SX28 or SX48 chips, you will see a carefully measured input impedance value quoted. The datasheet will mention the conditions for the measurement. It would have to be when the pin is in an input state and when the applied voltage is between 0V and 5V since voltages in excess of these would cause conduction in the protection diodes internal to each pin. The input circuit for I/O pins is usually a CMOS FET gate for the input side and two FETs, one from the pin to Vcc and the other from the pin to ground. These FETs are in a off state when the pin is an input, but have a bit of leakage current that contributes to the impedance of the I/O pin. The input FET gate also has a tiny bit of leakage that also contributes. The protection diodes are reversed biased so they won't conduct except for a tiny leakage current. These leakages are usually on the order of a small fraction of a microamp. Essentially, the high impedance and low input current is a function of the circuitry attached to the I/O pin. There should be no significant interaction between one I/O pin and any others. If you change the direction of an I/O pin to output, the output FETs will be enabled and one of them will conduct with low impedance (either to ground or to Vcc). They will pull the I/O pin to within 0.6V of the power supply "rail" (ground or Vcc) typically.
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