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Cycles and Simulator — Parallax Forums

Cycles and Simulator

metron9metron9 Posts: 1,100
edited 2006-08-12 11:56 in General Discussion
I just ordered the SX dev kit , I have been working with the atmel chips. I am looking at cycle times listed in the documents. After trying the simulator I have a question about cycle times.

The Document SXkeyMAN2 has the following:

When the pipeline is cleared, the fetch
and decode stages are replaced with ‘nop’ instructions. This effectively nullifies the invalid instructions
and increases the cycle-time for that command by 3 cycles.

the following code segment
Delay        clr    Count1          ;Initialize Count1, Count2                                    
        inc     count1
Loop        dec    Count1        ;Decrement until all are zero    
            jnz     loop




First I am trying to understand the cycle time listed as 1(4) to mean 1 or 4 depending on previous code. when would the cycle time be 4

When I simulate the code I see one cycle for 1 to 0 from 0 to 255 or any other number

The JNZ instruction changes the PC counter and adds NOP's to the pipeline but I only see 3 cycles for the JNZ instruction and one cycle for the DEC instruction.

I ask this because after reading the documents on the pipeline and looking at the cycle times I am wondering if 50Mhz is going to be any faster for typical code than the atmel 20Mhz chip with typical instructions of 1 cycle time.

The Simulator: Is there a simulator/debugger that stepps through code so you can see the code in context instead of just the instruction that will be executed next. Seems it would be hard to follow the code as you would have to look at a listing back and forth. The code above in the simulator shows a SZ instruction. I guess after looking a bit if your code jumps within a segment it compiles to one instruction vs another instruction.

This should be interesting as it seems to have a steeper learning curve than I originally thought it would have.

Looking forward to programming the SX chips.

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Comments

  • BeanBean Posts: 8,129
    edited 2006-08-12 01:30
    Cycle times of 1(4) means 1 cycle when using TURBO mode on the DEVICE line (your crazy if you don't) and 4 cycles if your NOT using TURBO.
    Note that the SX48 doesn't have a NON-turbo mode, it's ALWAYS in TURBO mode.

    Really all instructions are 1 cycle except jumps which are 3 cycles. Now some instructions are compound (are really more than 1 instruction).

    Trust me an SX at 50MHz will blow the doors off an Atmel @ 20MHz. And you can run the SX at 75MHz if needed.

    Bean.

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    ·
  • metron9metron9 Posts: 1,100
    edited 2006-08-12 04:52
    Sounds good Bean. I read most of the datasheet tonight, I am struck a bit by no push and pop instructions and the tiny default 2 level stack of course one would extend it to 8 levels I can't see why they even have the option of 2 levels, must be some reason.

    Do you just use the mov command to save and restore registers in sram?

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    Think outside the BOX!
  • BeanBean Posts: 8,129
    edited 2006-08-12 11:56
    The Non-turbo mode and the 2 level stack were options to make the SX function like the PICs of the day.
    No-one uses them anymore.

    Yes you just you MOV to save and restore to/from ram.

    Bean.

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    Cheap 4-digit LED display with driver IC·www.hc4led.com

    Low power SD Data Logger www.sddatalogger.com

    "You're braver than you believe, stronger than you seem, and smarter than you think" Christopher Robin to Pooh
    ·
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