MAX Address limit?
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Posts: 531
Hi all,
·In another thread, I have a link to an end stackable 1024bit I2C compatible EEPROM. My question, what would the theoretical internal HEX addressing limit be with the propeller?· With a "long" variable (32bits), calculated max value is 7FFF FFFF, and·with the 1024bit version,·
Reads may be
sequential within address boundaries 0000h to FFFFh
and 10000h to 1FFFFh. Functional address lines allow
up to four devices on the same data bus. This allows for
up to 4 Mbits total system EEPROM memory.
Now i'm new to understanding exactly how memory and addressing is "laid out" and how the two interact. I thought HEX only goes from 0 to F and begins a new cycle at 10 to 1F, what's that "h" for?
Does the theoretical max address have to include the three bytes for control and addressing w/a data array that is used for a page write opperation? The "h" in the memory address "FFFFh" and "1FFFFh" is as clear as mud to me as i never came across something like this. And i may have answered my own question, but I'd still like some clarifacation/vindication to my questions/statements, if anyone may shed a lil light on the subject, i'd much appreciate their help.
The only conclusion that I arive at right now is that a LONG would have no trouble with three bytes worth of control/chip address/memory address, and i realize you could split the control/chip address/read-write byte into a byte sized variable, but that's not the point here.· I've been eye'in up an NVRAM w/16M·on one chip. It sports 21 address lines and a similar·number of·datalines (parallel datalogging possible?)
Thanks again for all the help· guys,
Michael
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Definetly a E3 (Electronics Engineer Extrodinare!)
"I laugh in the face of imposible,... not because i know it all, ... but because I don't know well enough!"
·In another thread, I have a link to an end stackable 1024bit I2C compatible EEPROM. My question, what would the theoretical internal HEX addressing limit be with the propeller?· With a "long" variable (32bits), calculated max value is 7FFF FFFF, and·with the 1024bit version,·
Reads may be
sequential within address boundaries 0000h to FFFFh
and 10000h to 1FFFFh. Functional address lines allow
up to four devices on the same data bus. This allows for
up to 4 Mbits total system EEPROM memory.
Now i'm new to understanding exactly how memory and addressing is "laid out" and how the two interact. I thought HEX only goes from 0 to F and begins a new cycle at 10 to 1F, what's that "h" for?
Does the theoretical max address have to include the three bytes for control and addressing w/a data array that is used for a page write opperation? The "h" in the memory address "FFFFh" and "1FFFFh" is as clear as mud to me as i never came across something like this. And i may have answered my own question, but I'd still like some clarifacation/vindication to my questions/statements, if anyone may shed a lil light on the subject, i'd much appreciate their help.
The only conclusion that I arive at right now is that a LONG would have no trouble with three bytes worth of control/chip address/memory address, and i realize you could split the control/chip address/read-write byte into a byte sized variable, but that's not the point here.· I've been eye'in up an NVRAM w/16M·on one chip. It sports 21 address lines and a similar·number of·datalines (parallel datalogging possible?)
Thanks again for all the help· guys,
Michael
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Definetly a E3 (Electronics Engineer Extrodinare!)
"I laugh in the face of imposible,... not because i know it all, ... but because I don't know well enough!"
Comments
For your general question, a long is more than large enough to conveniently handle addresses up into 2GB range. Usually you construct the actual sequence of bytes needed to address the device "on the fly" from the long used to hold the address, but
you could hold a four byte control sequence in a long. I wouldn't recommend using a parallel memory. You'd use up all your I/O pins for address, data, and control lines and still not be able to address more than a megabyte. There is a 4MBit serial EEPROM (the AT45DB041) that uses SPI and maybe a 16MBit version as well. You could put maybe 4 of these on a piggyback board that would use only 8 I/O lines for access.
The "h" (or "H") stands for hexadecimal. Some programming languages use the convention of "d" for decimal and "b" for binary as well rather than using prefixes of nothing for decimal, "$" for hexadecimal, and "%" for binary.
Hope this clears the 'h' matter for you.
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Harley Shanko
h.a.s. designn
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Definetly a E3 (Electronics Engineer Extrodinare!)
"I laugh in the face of imposible,... not because i know it all, ... but because I don't know well enough!"
·· Actually it should be Serial Peripheral Interface and refers to a synchronous serial interface having anywhere from 2 to 5 wires.· I hope this helps.· Take care.
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Chris Savage
Parallax Tech Support
csavage@parallax.com
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Definetly a E3 (Electronics Engineer Extrodinare!)
"I laugh in the face of imposible,... not because i know it all, ... but because I don't know well enough!"
·· Correction...4 bits to a NIBBLE, 8 bits to a BYTE.·
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Chris Savage
Parallax Tech Support
csavage@parallax.com
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Definetly a E3 (Electronics Engineer Extrodinare!)
"I laugh in the face of imposible,... not because i know it all, ... but because I don't know well enough!"