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(*) Multiply in ASM — Parallax Forums

(*) Multiply in ASM

Direct Digital LabsDirect Digital Labs Posts: 27
edited 2006-07-28 21:56 in Propeller 1
On page 391 in the Propeller Manual it shows the "(*) Multiply and return lower 32 bits (signed)" then gives a ref to page 258 which is Spin.

Multiply (signed) is exactly what I nneed to do in ASM and I was wondering what the ASM syntax would be. I've tried just about everything.

I·need X * Y with the result in X.

If this is an error in teh manual how would I acchive the result in ASM??

-Dan

Comments

  • Mike GreenMike Green Posts: 23,101
    edited 2006-07-28 03:45
    There is no multiply instruction in the current Propellor. There is a thread with some examples of assembly subroutines that do multiplication and division originally posted by Chip.
  • Direct Digital LabsDirect Digital Labs Posts: 27
    edited 2006-07-28 03:54
    K, that's what I figured. I just now spotted in the Reserved list on P.419 "Mul & Muls" reserved for assembly. Those do not work either. I will try the multiplication from chip.

    Thanks,


    -Dan
  • Paul BakerPaul Baker Posts: 6,351
    edited 2006-07-28 20:38
    MUL and MULS are Prop 2 instructions.

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  • RsadeikaRsadeika Posts: 3,837
    edited 2006-07-28 20:50
    MUL and MULS are Prop 2 instructions.

    So, what does that mean, the Prop 2 part.
  • Mike GreenMike Green Posts: 23,101
    edited 2006-07-28 21:01
    Prop 2 is supposed to be the "next generation" Propeller chip. This is planned to include the MUL and MULS instructions and a couple of others in the manual marked as such. It's also supposed to include the second bank (B) of 32 I/O pins. Chip has been accumulating some other suggestions and ideas like changes to the phased lock loop (PLL) used in the CNTR registers. Whether there will be room for more RAM and ROM and how much is still up in the air.
  • Paul BakerPaul Baker Posts: 6,351
    edited 2006-07-28 21:56
    Prop 2 is the next generation chip, it is a work in progress.·The things which are already out of the bag:
    • 64 I/O pins
    • pipelined execution (1 instruction/ clock cycle)
    • single cycle·multiply (for those DSP applications needing·quick MAC operations)
    I know·some more particulars about it, but I'll adopt Chip's "It will be more of everything" saying. But if everything on the drawing board gets implemented, the Prop 2 will be a 8 fold increase in processing power, or 1.28 BIPS (billion instructions per second).

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