Fractional N Syntheizer (was High Frequency Distortion?)

IanM

Hi, I've just read the High Frequency Distortion? topic and was wondering if what is actually required is a fractional-N synthesizer. In order to implement that you would need a programmable divider after the fixed divide by 16. There should be enough bits in the CTRA/B register for this.

In a fractional-N synthesizer, the PLL has a fixed, relatively large reference frequency (say 100KHz), easy to achieve in the propeller, and a multi-order sigma-delta modulator (say 4th order).

A 4th order sigma-delta modulator consists of 4 accumulators feeding into each other and updates the programmable counter at the end of its count. That means the programmable divider is only being updated at the reference rate (ie 100Khz, when the PLL is locked), easy for the propeller.

The idea here is that the jitter experienced with a single accumulator is pushed out into the higher frequencies by virtue of the higher order accumulators and are then more easily reduced by the loop filter.

I think this is a perfect fit for the concept of the propeller, ie a little hardware and a fair bit of number crunching to solve a problem.

I recently built a synthesizer like this using a 20MHz AVR and a 74HC4046 with a fixed divide by 4 to generate any frequency between 10MHz and 20MHz with sub 1Hz resolution. I used one timer/counter to generate a fixed 100KHz reference and another timer/counter to count up the output from the VCO (via the divide by 4). The software used a 4th order 32 bit sigma-delta modulator, generated the next counter divide value, waited for the timer/counter to reach it's TOP value (whereupon the counter reset and started over) and then updated TOP with the new value.

Here's a reference that will help:
http://www.holmea.demon.co.uk/Frac2/Main.htm
http://www.holmea.demon.co.uk/Frac2/Mash.htm

BTW, what an amazing device the propeller is!

Cheers, Ian

cgracey

Ian,

This sounds fascinating! I read your text and looked at the links, but I don't have any handle on this yet. Does all this mean that we could quickly modulate the FRQ value in a CTR (via software) to get a lower-jitter output from the PLL? That would be awesome. That would make the PLLs much more useful for RF. Please try to help me understand this better.

Thanks.

(Later).... Oh, I see that this would require a programmable divider. This is something for the next generation chip. I really want to understand this MASH concept, because I suspect it could be applied to a number of things. Thanks for bringing this up.

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Chip Gracey
Parallax, Inc.

Post Edited (Chip Gracey (Parallax)) : 7/22/2006 6:13:02 AM GMT

IanM

Hi Chip,

I was wondering about that myself (your first paragraph), but (I'm not positve) but I don't think it's possible without a programmable divider in the loop - otherwise you'd need to module the PLL at the rate of the VCO/16.

Just thinking out loud now, but what if the VCO output is fed back to one of the counter inputs (is that possible and if so what is highest frequency)?

I need to think about this a bit more...

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Ian Mitchell
www.research.utas.edu.au

cgracey

Via an I/O pin, you could feed the·PLL back into another counter, but it will only be sampled on clock edges, so it will not function as a jitter-free divider. To do this will require real hardware. This can be done in the next generation. I still need to understand how this MASH stuff works. I will do some reading.

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Chip Gracey
Parallax, Inc.

IanM

Chip, (sorry to keep going on in this topic) I had the same cocerns with the AVR. It samples the input pins at the clock speed (ie 20MHz), but it didn't seem to affect the purity of the signal. I think what is happenning is the jitter in the sampling is much smaller that the variation generted by the sigma-delta modulator. The divider variation is about +-3 counts of the reference frequency. The jitter possibly has an effect similar to injected dither to improved SN ratios in A/D converters.

Even so, I still can't see how, without access to the reference side of the PLL, this will help. Looking forward to the next gereration!

Also I'd like to congratulate you on the descision to use DIP packages. I wish all chip manufactures had at least one version of their chips in a DIP package. It makes prototyping so much easier. And when space is not such an issue, is still fine for production runs in some cases.

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Ian Mitchell
www.research.utas.edu.au

IanM

IanM said...
Chip, (sorry to keep going on in this topic) I had the same cocerns with the AVR. It samples the input pins at the clock speed (ie 20MHz), but it didn't seem to affect the purity of the signal. I think what is happenning is the jitter in the sampling is much smaller that the variation generted by the sigma-delta modulator. The divider variation is about +-3 counts of the reference frequency. The jitter possibly has an effect similar to injected dither to improved SN ratios in A/D converters.

Even so, I still can't see how, without access to the reference side of the PLL, this will help. Looking forward to the next gereration!

Also I'd like to congratulate you on the descision to use DIP packages. I wish all chip manufactures had at least one version of their chips in a DIP package. It makes prototyping so much easier. And when space is not such an issue, is still fine for production runs in some cases.

--
I meant the signal side (as well as the reference side) of the PLL.

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Ian Mitchell
www.research.utas.edu.au