Multiple Interrupt Codes

Steel

Can you have multiple interrupt codes in the SX?

The reason I ask is because it looks like the Interrupt code needs to be placed at address 0x00 in memory, and all the examples (Interrupt_B, Interrupt_RTCC1, Interrupt_RTCC_2) only demonstrate 1 Interrupt.

I have a project that is using 2 pins as interrupts.· RB.0 and RB.3.· If there is a rising Edge on RB.0, I would like one Interrupt Routine to occur.· If there is a rising Edge on RB.3, I would like a different Interrupt routine to occur.

Also...If I want to use RB.3 in another part of code to perform a different interrupt...

Is this possible?· I am still getting familiar with the SX Chip and need more information.

Thanks
Shaun

Post Edited (Steel) : 7/21/2006 2:23:44 PM GMT

PJMonty

Shaun,

The SX only has one interrupt vector, which is at location 0x00 as you noted. This means that the same code is invoked for any interrupt source you have, and it's up to that code to determine (via software) what source generated the interrupt. One tricky thing is that you can only safely have a single interrupt source without the risk of losing interrupts. Go to question #6 in this FAQ as it explains the issue in more detail:

www.parallax.com/sx/support_faqs.asp

Thanks, PeterM

Bean

Shaun,
As Peter explained, the same interrupt routine is called for ALL interrupts.

If the interrupt from RB.0 occurs and the interrupt code is running when the interrupt occurs on RB.3, the new interrupt will not be noticed until the 1st interrupt code is complete. Then the SX will immediately run the interrupt routine again for the new (RB.3) interrupt.

So the 2nd interrupt is not lost, it's just delayed.

Of course your code must handle this situation.

Bean.

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PJMonty

Bean,

Actually, the SX can definitely "lose" an interrupt. When an interrupt happens, the first thing the SX chip does in servicing it is to turn off responding to interrupts. If a new interrupt occurs before the current handler finishes executing, then the new interrupt will be lost. Even if you re-enable interrupt servicing as the first step in your interrupt code handler, you could always have an interrupt happen in the tiny space between the first interrupt happening and the servicing re-enabled. Check out the URL in my previous post for the details.

Thanks, PeterM

Rsadeika

To use an example, lets say you have a UART VP running, and you also have RB0 set for rising edge, as soon as RB0 is "tripped" all other activity is stopped, and the code associated with RB0 is started. So, if your UART is in the middle of data transmision, it stops, the UART VP that is. The RB0 runs, and after it is done, it stops and the UART VP starts again. At this point I do not believe that it has the ability to figure what or how much data got away, so in essence, it has lost data. It also sounded like the edge detection has a higher priority. When I was reading the documentation I got the impression that you do not want to have things like VPs running at the same time that you are using the edge detection. I could be wrong about this, so if I am all wet ...

Ray

Bean

PeterM,
Okay, they mean if another interrupt "ON THE SAME PIN" occurs it will be lost. That I agree with.
But if an interrupt on RB.0 is in progress and an interrupt on RB.3 occurs it will be run as soon as the RB.0 interrupt is finished.
As long as you only clear the bit of the interrupt you are processing in the pending register.

Bean.

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Low power SD Data Logger www.sddatalogger.com

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PJMonty

Bean,

I'll have to defer to you there as I have never tried to see if multiple bits will stay pending. I assume you are correct.

However, if you have an edge detect as an interrupt source and the RTCC as another interrupt source, my understanding from the documentation is that if either one is being serviced and the other interrupt occurs, that new interrupt will be lost.

Thanks, PeterM

pjv

Hi All;

The SX 28 has eight individual PENDING bits for the RB level change detection, but not for the RTCC.

The SX 48 has the RB PENDING bits also, as well as an overflow (same as PENDING) bit on the RTCC. So this device give some more capability in this area.

Cheers,

Peter (pjv)

Bongo

Re interrupt vectors, I note that a wake up interrupt is not being used here, however a wakeup interrupt will jump to the reset vector, not 0x00.

Therefore, all interrupts do not actually point to the same location.



bongo

pjv

Hi Bongo;

I guess you are somewhat right, but perhaps waking up from sleep might not be called an interrupt. Afterall, it WAS sleeping, so we're not really interrupting anything. On top of that, only a true SX interrupt saves the state of numerous registers, and restores them on exiting interrupt. Reset (wake up from sleep) has no such ability. So, perhaps they are very different afterall.

Cheers,

Peter (pjv)

Bongo

Ooooh, you've got me there PJV.· Checking the SX manual index the questionable item is written as "wake up interrupt".· I do believe this terminoligy has lodged itself inside my brain, with no applicable questioning by myself.



bongo