Propeller Land Patterns?
![Phil Pilgrim (PhiPi)](https://forums.parallax.com/uploads/userpics/612/nMG83RHE7MV61.gif)
I haven't located any recommended PCB pad dimensions in the Propeller docs — only package dimensions. Can anyone recommend a source of this data for both the QFN and LQFP packages? (My CAD software includes ten different QFP-44 layouts, and no QFN-44's.)
Thanks,
Phil
Thanks,
Phil
Comments
For the QFN, there are a few things to consider. Foremost, you need an exposed copper pad on your PCB to mate up with the big square in the middle of the chip. The copper pad should mate to the chip 1:1 and be grounded. Another critical thing you need is a paste mask that deposits paste on only 1/2 of the area of this square pad - do this in quarters. You don't want the chip to float too high on solder and miss its pin connections. For the pins, just make sure you cover them 1:1 with copper pads, with a little extra copper going away from the chip so that you'll be able to see the joints. The paste mask should deliver copper to the entire pin pads (unlike the 1/2 coverage required by the big middle square pad).
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Chip Gracey
Parallax, Inc.
A couple of most informative documents I've found online are,
www.freescale.com/files/analog/doc/app_note/AN1902.pdf
which shows a 9mm QFN, but it is a 64 pin chip with lands on 0.5mm centers.
I think the Propeller QFN is 9mm with 44 pins on 0.65mm centers. These documents talk about how some QFNs have the lands exposed on the edge of the package, and some don't (depends on sawed vs punched singulation). It seems like the advantage of the exposed end is that it can form a fillet that you can inspect visually after soldering. Otherwise, its x-rays and crossed fingers.
www.amkor.com/products/notes_papers/Board_Level_QFN.pdf
has a lot of experimental reliability test information based on different soldering and land parameters.
They both go into the considerations about islands of solder coverage on the center pad. They also recommend vias under the central pad through to the ground plane for thermal reasons, with no thermal isolators. The vias should be covered with solder mask to prevent down wicking of solder during reflow.
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Tracy Allen
www.emesystems.com
Chip Gracey
Parallax, Inc.