WAITPEQ Timing, Setup & Hold Times, etc.

Phil Pilgrim (PhiPi)

Chip,

Given this code:

        [b]waitpeq[/b]   one, one
        [b]mov[/b]       dest, [b]ina[/b]
        ..
one     [b]long[/b]      1

and this diagram:



can you indicate where ina is read by the mov? What are the port pin setup and hold times for the waitpeq relative to the clock? For the mov?

Thanks,
Phil

Paul Baker

Four stage pipelines typically are read, decode, execute, write so mov should record ina the 3rd cycle of the clock for the instruction. Though Im not positive, I think it would be recorded at edge c.

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1+1=10

pjv

Hi Phil;

I'll try to answer part of this........... to the best of my recollection:

When the waitpeq instruction is started, it stalls after its second clock. Then when the condition becomes true, the rise of A0, it takes three more clocks to finish the instruction, so that would consume clocks a,b,c. As Paul said, the next instruction wil read the port during the third clock, f.

At this moment, I'm not recalling if instructions conclude on the rise or fall of the clock, but I'll check that out, and confirm my findings for you later today.

Regrettably, I don't know the set-up and hold times; it would take a bunch of work to determine that emperically.

Cheers,

Peter (pjv)

cgracey

The COGs go through the following state sequence, advancing each clock cycle:

0) read source N

1) read destination N

2) read instruction N+1

x) any wait cycles go here (0...infinity clocks)

3) write destination N (N=N+1, goto 0)

So, the source is read 3 cycles before the destination result it written. This timing scheme gives the ALU·two clocks in which to settle after I, S, and D have been read.


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Chip Gracey
Parallax, Inc.

william chan

Can a cog wait on 2 or more pins simultaneously?

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Phil Pilgrim (PhiPi)

Yes. It's done with a bitmask to select the pins you want to monitor. You can wait for the selected pins either to equal a certain pattern, or to differ from it.

-Phil

MagIO2

Don't want to hitchhike the currently running WAITPEQ thread, so I digg this one out to ask my question ;o) ... and the question is only for understanding what's going on in a COG.

1. Shouldn't 2) be read instruction N+1 and execute N ?
2. For me this sounds like the start of a PASM needs one additional instruction because the first instruction is fetched with the first cycle but executed with the second cycle. So, is the PC maybe set to adress 511 at the beginning of PASM code execution?

Rayman

I would imagine that the execute part really begins once the source is read... It's probably latched on step 2 so that the new instruction doesn't change it...

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MagIO2

@ray:
Don't agree with that.

0) To execute the instruction you need source and destination. If you say AND x,y it makes no sense to start execution if you did not read x yet.
1) execute the instruction here would mean that you don't have to flush the pipeline for conditional jumps because in step 2 it would be clear which instruction to fetch next.
So, for me 2) is the place where I'd expect the execution.

Rayman

Well, I think it's a little philisophical... I think some some things are set when the new instruction is read, some things are set when the source is read, and the result appears shortly after the destination is read... I'm guessing the actual execution is asyncronous, and some instructions would take longer than other so settle to a result... But, unless there are hidden registers, I think the result has to be latched when the new instruction is read...

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Ale

Hei,

do not forget this discussion we had last year:

http://forums.parallax.com/showthread.php?p=725782

With oscillograms and all

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