74HC595 to drive leds

ktekx

bear with me, as i'm inexperience with digital. I was looking at the 74HC595 IC and was confused about a couple of things. When they refer to "stages," is that how many data registers can be held at any given time? And the "latch" line refers to pulling the next register in line out to be displayed? I'm trying to figure this out so I can try and drive a couple of LEDs just for learning purposes right now. Maybe somebody can explain this whole concept in more simpler terms?

Jon Williams

Download our StampWorks book -- it will show you how to use the '595, and to cascade them if you want more than eight outputs.

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Jon Williams
Applications Engineer, Parallax

ktekx

Thanks Jon, this brings me to some questions, though. What does the data sheet mean when they say "states" (ex. 3-state). Also, when cascading, how does the shift register know how many registers to "fill up" before it loads the data into its own register? For example, if there were 4 shift registers in cascade, how would the 3rd one know that it is to "save" the shifted data into its own register or to ignore it?

Jon Williams

An I/O pin can have three states: output low, output high, or input (high-z).

The '595 is a dumb device. It takes serialized bits in one end and pumps them out the other. When the latch pin is pulsed the bits that are currently stored inside get transferred to the outputs. It is up to the programmer to keep everything aligned.

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Jon Williams
Applications Engineer, Parallax

ktekx

But if you have two '595's cascaded, as in the example, and you have two SHIFTOUT's in a row, wouldn't the device furthest from the Stamp get the second SHIFTOUT's data bits since it's the last one shifted out? I guess it's confusing me because there's no "addressing" aspect in loading data registers to multiple chips.

I'm really sorry for stretching this out more than it has to be!!

PJAllen

OK -- 2 595s are "cascaded", one derives its data from the STAMP and the other gets its from the 595 that's down-stream, the Q_H to DATA IN connection.· The DATA advances with each CLK·pulse.· Say, you're bipping one bit through.··When it appears as a HI at·Q_H of the down-stream 595 is when it can be snagged by the one ahead of it.

The LATCH freezes the DATA that was in the 595 at the time LATCH goes active.· The output enable (/OE) places the DATA on the outputs.· Think of it as a switch (8 switches) inside the 595 between the registers and the output pins.

Stampworks V2· pages 134-136 has an excellent example of this cascading deal, so have a bash (will ya?).· Maybe placing an LED on the LATCH and CLOCK might help you understand a bit more (??).

Post Edited (PJ Allen) : 4/19/2006 8:40:42 PM GMT

ktekx

ohhh, makes perfect sense to me now. Crystal clear, thanks Jon and PJ Allen!