Would multiple virtual ADCs be possible?

LoopyByteloose

Would·one or two COGs [noparse][[/noparse]two would alternate polling] be able to operate as Analogue to Digital converters?
The concept is to have something like 4 or 8 pins working as ADC inputs.

Am I dreaming?

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cgracey

No problem.
Using the CTR modules (two in each COG), you could perform the fastest A/D, without resorting to a discrete ADC chip. Using the CTR modules requires a cap and a resistor per ADC, plus an optional input resistor to set the voltage gain. Each such ADC channel uses two pins and works by using negative feedback to balance a pin at its logic threshold. The more 'low' feedback required, the more positive the input, and vice-versa. at 80 MHz, there is a 12.5ns feedback loop. This results in 312.5k samples per second (ksps) at 8 bits, or 19.5ksps at 12 bits, and so on. The slower the sample rate, the higher the resolution. The relationship between sample rate and bit resolution is: sample rate·= 80M / 2^n, where n is number of bits.
Each COG has two CTR modules which can each perform one channel of high-speed conversion. If you can get by with reduced sample rates, you could have one COG perform as many channels as you want, purely in software, and not rely on the CTRs.

Kramer said...
Would·one or two COGs [noparse][[/noparse]two would alternate polling] be able to operate as Analogue to Digital converters?
The concept is to have something like 4 or 8 pins working as ADC inputs.

Am I dreaming?

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Chip Gracey
Parallax, Inc.

KevinB

Chip,

could you elaborate please on details of the ADC? I'm 'familiar' with electronics but not enough to know what you have in mind for this. Thanks.

Luis Digital

View: AN001 - Propeller Counters
http://www.parallax.com/propeller/downloads.asp

Bergamot

Chip Gracey (Parallax) said...
No problem.
Using the CTR modules (two in each COG), you could perform the fastest A/D, without resorting to a discrete ADC chip. Using the CTR modules requires a cap and a resistor per ADC, plus an optional input resistor to set the voltage gain. Each such ADC channel uses two pins and works by using negative feedback to balance a pin at its logic threshold. The more 'low' feedback required, the more positive the input, and vice-versa. at 80 MHz, there is a 12.5ns feedback loop. This results in 312.5k samples per second (ksps) at 8 bits, or 19.5ksps at 12 bits, and so on. The slower the sample rate, the higher the resolution. The relationship between sample rate and bit resolution is: sample rate = 80M / 2^n, where n is number of bits.
Each COG has two CTR modules which can each perform one channel of high-speed conversion.

Does anyone know at what point the least significant bits become useless noise?

Mike Green

This depends a lot on the wiring and there's no nice, neat answer. The closer you get the cap and resistor to the chip the better. There's a little improvement if the two pins used are not physically adjacent and the pin between is electrically quiet. There was a discussion thread on this subject a couple of months ago, around the time the ADC objects were posted. Do some forum searching for it. I think the subject came up again in the discussion around the Prototype Board.

Gadgetman

Take a look at this thread:
http://forums.parallax.com/forums/default.aspx?f=25&m=159341&g=160497

I'm going to use this routine(but with both counters to get two channels at a time, and also alternating between different inputs to get 8 or more channels as I won't be needing better than 8 or 10bit, at 100Hz or so)

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