On December 9th, 2004, a thread entiltled 'The Secret SX Instructions' was started by pjv.
I think it applied to what Bean is trying to express. The ISR requires a set of duplicate registers in order to fulfill its mission [noparse][[/noparse]to reinstate the system]. From what I can glean, this is done by having the system intially write to two registers - the commonly visable, and a shadow - when all is functioning normal. That would allow the system to operate deterministically. Then, when an interupt is evoked, the shadow retains the 'systems status' while the visable registers are used to process whatever is required. On a ISR return, the shadow registers are read to get back to the main program.
pjv DOES mention that there are more registers included in the SX48s shadow registers [noparse][[/noparse]aka the shadow stacks] and Mode registers may even be included.
Does this have anything to do with the tricky Bank 0/ Bank 1 indirect addressing?
Or am I just making the world more complicated?
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"When all think alike, no one is thinking very much.' - Walter Lippmann (1889-1974)
······································································ Warm regards,····· G. Herzog [noparse][[/noparse]·黃鶴 ]·in Taiwan
if you have my book handy, please have a look at Chapter 2.2.2.2 in Section II - Reference, pages 205 ff (in the 1st edition, the page number may be different).
There you find an explanation how to address the various parts of the SX48/52 RAM. I must admit - reading it now again gives me the feeling that I should re-work it for easier reading (and understanding) but if you go through the text a couple of times, following the graphic representation on page 205, I hope you understand what I wanted to explain.
Kramer,
I hope I will express myself as politely as possible here... from the many posts you place, I have the impression that you spend a lot of your valuable time reading all the other posts here in the forum, and I allege that you only have honest reasons placing your comments. On the other hand, these comments can only be helpful for other posters looking for help when they contain substantial information. Guesswork, vague, or non-topic-related information might even mis-lead the other poster. Please check the posts you have made to this thread with self-criticism, and you'll understand what I mean:
"If you are not using the additional ports, maybe they can function as global RAM...." - this is mis-leading:
The principle of "global registers" is valid for the SX48/52 as is for the "small" SXes with the only difference that two additional I/O ports are mapped into this area. Using or not using these ports does by no means change the global characteristic of this memory block. In question here is how one can switch between the global registers, and Bank 0 in an SX48/52.
"Personally, I know that Bean has a lot of experience and there are some things that have escaped publication.
One of the SX 2005 contest awards was for work on a RTO using undocumented registers...."
Here, you bring up a topic that has absolutely nothing to do with the problems discussed here at all. Throwing this in here, can only lead to more confusion.
"On December 9th, 2004, a thread entiltled 'The Secret SX Instructions' was started by pjv.
I think it applied to what Bean is trying to express. The ISR requires a set of duplicate registers in order to fulfill its mission...."
Again, this does not help by any means explaining how to address the SX48/52 RAM which is the question here (besides the fact that the "mysterious secret SX instructions and registers" are not SX48/52-specific - they are available in the "smaller" SXes as well).
Kramer, please get me right, by no means do I want to offend you - it is just a well-meant advice: Instead of spending your time writing posts w/o useful background, why don't you read through the SX docs you have on hand (where my book may be just one source, and not always the best) or are available on the net, and then come up with a helpful source of information? This will help others, looking for help, and - as a side-effect - helps you to gain more understanding for the SX or any other topics.
Guenther,
Please don't feel the need to apologize.
Bean brought up something that I really don't understand and haven't be able to sort out on my own [noparse][[/noparse]which I indend to do].
Posting at this technical level does require one to be diligent in maintaining clarity for everyone's benefit.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
"When all think alike, no one is thinking very much.' - Walter Lippmann (1889-1974)
······································································ Warm regards,····· G. Herzog [noparse][[/noparse]·黃鶴 ]·in Taiwan
this is fine with me - so if you don't understand the memory addressing scheme of the SX48/52, my suggestion is to just follow this thread, and place questions belonging to this topic if necessary. If you have questions to the secret insrtuctions/registers, it would be off-topic to place them here. Either find a thread dealing with them (there is at least one), or open a new one.
If you study the Ubicom product bulletins on the SX48/52 CARFULLY and THOROUGHLY it explains the memory model. I agree however it is somewhat burried and cryptic.
I would further suggest that to FULLY understand what goes on in this '48/52 chip (as well as the SX28), you NEED to EXPERIMENT with it. Don't expect to get a full comprehension of their detailed vagaries without some sort of programming board, an SX-Key, tons of time, and excruciating will and persistence.
That's how the rest of us get to know what we know......... just LEARN it!
Also, (in my opinion only), if you don't own an SX48/52 and a SX-Key, in other words the ability to try out what you're asking help in, then you really ought not be asking detailed questions as the answers will be much less meaningful, and you are then largely wasting the forum's time.
Sorry to be so blunt, but I get frustrated with "loose questions" that the poster could easily determine himself if only he would bother!
I further get frustrated by posters asking questions about their code without posting their TOTAL code. It's extra hard·trying to figure out what is
going on in code (often not well documented to boot) without being able to see the whole picture. The poster's assumptions·as to·"what is important" about their problem are often not well founded, and its really some other obscurity that is the culprit. This wastes a lot of our time.
I have largely given up helping posters who don't bother to give me a good description of what the're trying to accomplish, what EXACTLY is the problem, what they've tried, and their whole code.
Especially now, with the advent of the Propeller, my time is very limited, and I'll only help those who are thoughtful and appreciative of the value of my time.
Comments
I think it applied to what Bean is trying to express. The ISR requires a set of duplicate registers in order to fulfill its mission [noparse][[/noparse]to reinstate the system]. From what I can glean, this is done by having the system intially write to two registers - the commonly visable, and a shadow - when all is functioning normal. That would allow the system to operate deterministically. Then, when an interupt is evoked, the shadow retains the 'systems status' while the visable registers are used to process whatever is required. On a ISR return, the shadow registers are read to get back to the main program.
pjv DOES mention that there are more registers included in the SX48s shadow registers [noparse][[/noparse]aka the shadow stacks] and Mode registers may even be included.
Does this have anything to do with the tricky Bank 0/ Bank 1 indirect addressing?
Or am I just making the world more complicated?
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
"When all think alike, no one is thinking very much.' - Walter Lippmann (1889-1974)
······································································ Warm regards,····· G. Herzog [noparse][[/noparse]·黃鶴 ]·in Taiwan
Post Edited (Kramer) : 3/19/2006 3:49:54 PM GMT
No the shadow registers are something completely different.
Bean.
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"SX-Video·Module"·available from Parallax for only $28.95 http://www.parallax.com/detail.asp?product_id=30012
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Product web site: www.sxvm.com
"Wise men know when they're right. The wisest also·know when they're wrong."
·
if you have my book handy, please have a look at Chapter 2.2.2.2 in Section II - Reference, pages 205 ff (in the 1st edition, the page number may be different).
There you find an explanation how to address the various parts of the SX48/52 RAM. I must admit - reading it now again gives me the feeling that I should re-work it for easier reading (and understanding) but if you go through the text a couple of times, following the graphic representation on page 205, I hope you understand what I wanted to explain.
Kramer,
I hope I will express myself as politely as possible here... from the many posts you place, I have the impression that you spend a lot of your valuable time reading all the other posts here in the forum, and I allege that you only have honest reasons placing your comments. On the other hand, these comments can only be helpful for other posters looking for help when they contain substantial information. Guesswork, vague, or non-topic-related information might even mis-lead the other poster. Please check the posts you have made to this thread with self-criticism, and you'll understand what I mean:
"If you are not using the additional ports, maybe they can function as global RAM...." - this is mis-leading:
The principle of "global registers" is valid for the SX48/52 as is for the "small" SXes with the only difference that two additional I/O ports are mapped into this area. Using or not using these ports does by no means change the global characteristic of this memory block. In question here is how one can switch between the global registers, and Bank 0 in an SX48/52.
"Personally, I know that Bean has a lot of experience and there are some things that have escaped publication.
One of the SX 2005 contest awards was for work on a RTO using undocumented registers...."
Here, you bring up a topic that has absolutely nothing to do with the problems discussed here at all. Throwing this in here, can only lead to more confusion.
"On December 9th, 2004, a thread entiltled 'The Secret SX Instructions' was started by pjv.
I think it applied to what Bean is trying to express. The ISR requires a set of duplicate registers in order to fulfill its mission...."
Again, this does not help by any means explaining how to address the SX48/52 RAM which is the question here (besides the fact that the "mysterious secret SX instructions and registers" are not SX48/52-specific - they are available in the "smaller" SXes as well).
Kramer, please get me right, by no means do I want to offend you - it is just a well-meant advice: Instead of spending your time writing posts w/o useful background, why don't you read through the SX docs you have on hand (where my book may be just one source, and not always the best) or are available on the net, and then come up with a helpful source of information? This will help others, looking for help, and - as a side-effect - helps you to gain more understanding for the SX or any other topics.
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Greetings from Germany,
G
Cheers,
Peter (pjv)
Please don't feel the need to apologize.
Bean brought up something that I really don't understand and haven't be able to sort out on my own [noparse][[/noparse]which I indend to do].
Posting at this technical level does require one to be diligent in maintaining clarity for everyone's benefit.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
"When all think alike, no one is thinking very much.' - Walter Lippmann (1889-1974)
······································································ Warm regards,····· G. Herzog [noparse][[/noparse]·黃鶴 ]·in Taiwan
Post Edited (Kramer) : 3/24/2006 4:40:43 AM GMT
this is fine with me - so if you don't understand the memory addressing scheme of the SX48/52, my suggestion is to just follow this thread, and place questions belonging to this topic if necessary. If you have questions to the secret insrtuctions/registers, it would be off-topic to place them here. Either find a thread dealing with them (there is at least one), or open a new one.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Greetings from Germany,
G
If you study the Ubicom product bulletins on the SX48/52 CARFULLY and THOROUGHLY it explains the memory model. I agree however it is somewhat burried and cryptic.
I would further suggest that to FULLY understand what goes on in this '48/52 chip (as well as the SX28), you NEED to EXPERIMENT with it. Don't expect to get a full comprehension of their detailed vagaries without some sort of programming board, an SX-Key, tons of time, and excruciating will and persistence.
That's how the rest of us get to know what we know......... just LEARN it!
Also, (in my opinion only), if you don't own an SX48/52 and a SX-Key, in other words the ability to try out what you're asking help in, then you really ought not be asking detailed questions as the answers will be much less meaningful, and you are then largely wasting the forum's time.
Sorry to be so blunt, but I get frustrated with "loose questions" that the poster could easily determine himself if only he would bother!
I further get frustrated by posters asking questions about their code without posting their TOTAL code. It's extra hard·trying to figure out what is
going on in code (often not well documented to boot) without being able to see the whole picture. The poster's assumptions·as to·"what is important" about their problem are often not well founded, and its really some other obscurity that is the culprit. This wastes a lot of our time.
I have largely given up helping posters who don't bother to give me a good description of what the're trying to accomplish, what EXACTLY is the problem, what they've tried, and their whole code.
Especially now, with the advent of the Propeller, my time is very limited, and I'll only help those who are thoughtful and appreciative of the value of my time.
Cheers,
Peter (pjv)
Post Edited (pjv) : 3/24/2006 4:15:16 PM GMT