TLC540IN Analog to Digital converter

marzec309 · 2006-03-03 14:48

hello,
I just got my hands on a TLC540IN A/D converter. I am having a little problem interfacing this with my BS2. The data sheet states that the system clock and the in out clock can be tied together to minimize control points. but with this set up i am having a problem writing code for it. I can get the A/D to work but i cannot get the A/D's address to change.

here is a sample of the code i have right now:

sample:
address = 0
LOW ad ' chip select

FOR counter = 0 TO 1
HIGH clock_pin ' system clock and I/O clock
PAUSE time
LOW clock_pin ' system clock and I/O clock
PAUSE time
NEXT

SHIFTOUT address_pin , clock_pin, 0, [noparse][[/noparse]address\4]

FOR counter = 0 TO 3
HIGH clock_pin ' system clock and I/O clock
PAUSE time
LOW clock_pin
PAUSE time ' system clock and I/O clock
NEXT

HIGH ad

FOR counter = 0 TO 35
HIGH clock_pin ' system clock and I/O clock
PAUSE time
LOW clock_pin ' system clock and I/O clock
PAUSE time
NEXT

HIGH ad

RETURN

get_reading:

LOW ad ' chip select
SHIFTIN serdata_in, clock_pin, 0, [noparse][[/noparse]adc\8]
HIGH ad ' chip select

RETURN

here is a link to the A/D's Data Sheet:

http://focus.ti.com/lit/ds/symlink/tlc541.pdf

marzec309 · 2006-03-03 17:22

I found out that the TLC540IN is a direct replacement for a ADC0811.

marzec309 · 2006-03-03 18:31

after studying the data sheet i beleive my timing is off, because i don't think the Multiplexer is recognizing the chip select.

Jon Williams · 2006-03-03 18:52

The way I see the data sheet you send the address on one cycle, then read the data for that cycle on the next.· I don't have the part to test, but this would be my inclination:

Read_ADC:
··LOW CS
· SHIFTOUT·AddrOut, Clock, MSBFIST, [noparse][[/noparse]address\4]
· HIGH CS
· LOW CS
· SHIFTIN DataIn, Clock, MSBPRE, [noparse][[/noparse]adcData]
· HIGH CS
· RETURN·

Note that I wrote this on-the-fly and it's up to you to work out any kinks.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Jon Williams
Applications Engineer, Parallax

marzec309 · 2006-03-04 22:40

Ok after studying the data sheet more this is the code i came up with. From what i can see. There is no reason why it wont work but it doesn't. Could it be that this chip is not campatable with the BS2.

clock         PIN     7       'A/d pin 19 and 18
address     PIN     8       'A/D pin 17
ser_data    PIN     9       'A/D pin 16
cs             PIN     10      'A/D pin 15 pulled up to Vdd per Data Sheet (10K resistor)

Counter     VAR     Byte    'Variable for clock Pulse
adc           VAR     Byte    'A/D Data

address = %1011             'Self Test Address

main: 
  LOW cs                                                                'Activate Chip Select

  FOR counter = 0 TO 1                                           '
    PULSOUT clock, 1                                               'Reconize Chip Select
  NEXT                                                                   '

  SHIFTOUT address, clock, MSBFIRST, [noparse][[/noparse]address\8]   'Shift Address To A/D

  HIGH cs                                                               'Deactivate Chip Select

  FOR counter = 0 TO 35                                          '
    PULSOUT clock, 1                                                'A/D Coversion Time
  NEXT                                                                   '

  LOW cs                                                                'Activate Chip Select

  SHIFTIN ser_data, clock, MSBPRE, [noparse][[/noparse]adc]                 'Read Data From A/D

  HIGH cs                                                               'Deactivate Chip Select

  DEBUG HOME, DEC ? adc,                                     'Print Data
              BIN8 ? adc                                               '

PAUSE 25
GOTO main
END

here is the data sheet agian:
focus.ti.com/lit/ds/symlink/tlc541.pdf

PJAllen · 2006-03-04 23:42

You have --

main: 
  LOW cs                                          ' Activate Chip Select

  FOR counter = 0 TO 1                            '
    PULSOUT clock, 1                              ' Reconize Chip Select
  NEXT                                            '

  SHIFTOUT address, clock, MSBFIRST, [noparse][[/noparse]address\8]  ' Shift Address To A/D

  [color=red]HIGH cs[/color]                                         ' Deactivate Chip Select

  FOR counter = 0 TO 35                           '
    [color=red]PULSOUT clock, 1[/color]                              [color=red]' A/D Coversion Time[/color]
  NEXT                                            '

  LOW cs                                          ' Activate Chip Select

  SHIFTIN ser_data, clock, MSBPRE, [noparse][[/noparse]adc]          ' Read Data From A/D

  HIGH cs                                         ' Deactivate Chip Select

Versus...

"The conversion cycle, which requires 36·SYSCLKs, is initiated on the 8th falling edge of I/O CLK after /CS goes low for the Chan. whose Addr. exists in Mem at that time. If /CS is kept low during conversion, I/O CLK must remain low for at least 36 SYSCLKs to allow conversion to be completed."

marzec309 · 2006-03-05 00:06

but how can cs go low when it is already low.
if it is turned high then low again it would reset the convertion cycle.

marzec309 · 2006-03-05 00:15

ok to let you know the i/o clcok and the sys clock are tied togeather the cs high disables the i/o clock so the 36 clock pulses are only reconized by the sys clock. (i think, it's got me stumped)

marzec309 · 2006-03-05 00:18

page 10 of the Data sheet states that the I/O clock and the sys clock can be tied togeather. this would be the only way with BS2 because it has no sys clock

marzec309 · 2006-03-05 00:34

i believe my problem is in the first part of the code(reconize chip select). because i can get the chip to do the convertion, and output that data. but i canot get it to change the address.

PJAllen · 2006-03-05 00:42

·This is no good then?

  [color=red]LOW cs[/color]                                        ' activate Chip Select
  FOR counter = 0 TO 35
    PULSOUT clock, 1                            [color=red]' A/D Coversion Time[/color]
    NEXT                                        '

  SHIFTIN ser_data, clock, MSBPRE, [noparse][[/noparse]adc]        ' Read Data From A/D

  HIGH cs                                       ' Deactivate Chip Select

Sorry, I don't have one of these on hand.· I thought my quote indicates the /CS (cs) must be active (active low) before starting conversion time.
[noparse][[/noparse] I'll go back and sit in the cheap seats. ]

Post Edited (PJ Allen) : 3/5/2006 12:45:17 AM GMT

marzec309 · 2006-03-05 01:11

Well i tried you idea. no luck. I believe that by be a type-o, because of this section from the data sheet.

1. CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edges
and then a falling edge of SYSTEM CLOCK after a low CS transition, before the low transition is recognized.
This technique is used to protect the device against noise when the device is used in a noisy environment.
The MSB of the previous conversion result automatically appears on DATA OUT.
2. A new positive-logic multiplexer address is shifted in on the first four rising edges of I/O CLOCK. The MSB
of the address is shifted in first. The negative edges of these four I/O clock pulses shift out the second, third,
fourth, and fifth most significant bits of the previous conversion result. The on-chip sample and hold begins
sampling the newly addressed analog input after the fourth falling edge. The sampling operation basically
involves the charging of internal capacitors to the level of the analog input voltage.
3. Three clock cycles are then applied to I/O CLOCK and the sixth, seventh, and eighth conversion bits are
shifted out on the negative edges of these clock cycles.
4. The final eighth clock cycle is applied to I/O CLOCK. The falling edge of this clock cycle completes the
analog sampling process and initiates the hold function. Conversion is then performed during the next 36
system clock cycles. After this final I/O clock cycle, CS must go high or the I/O CLOCK must remain low
for at least 36 system clock cycles to allow for the conversion function.

now because SYS Clock and I/O clock are tied to geather CS can not be set low because i need the clock signal to control the convertion. If it were LOW i would pulse the I/O clock and stop the convertion(The I/O clock is disabled when CS is HIGH). judjing by the statment above this is alowable.

Now by no means was i saying your wrong. I'm too new at this to jump to conclutions. i just read the dada sheet so many times now I almost know it word for word.

thanks for you help

marzec309 · 2006-03-05 20:25

Well, today i sent an e-mail to Texas Instruments tech support. I don't know if they will help or not, because i dont plan on using this A/D for a production run. But it doesn't hurt to try. If they help me solve the problem. I will post the results here for others to use.

mike

TLC540IN Analog to Digital converter

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