TLC540IN Analog to Digital converter
hello,
I just got my hands on a TLC540IN A/D converter. I am having a little problem interfacing this with my BS2. The data sheet states that the system clock and the in out clock can be tied together to minimize control points. but with this set up i am having a problem writing code for it. I can get the A/D to work but i cannot get the A/D's address to change.
here is a sample of the code i have right now:
sample:
address = 0
LOW ad ' chip select
FOR counter = 0 TO 1
HIGH clock_pin ' system clock and I/O clock
PAUSE time
LOW clock_pin ' system clock and I/O clock
PAUSE time
NEXT
SHIFTOUT address_pin , clock_pin, 0, [noparse][[/noparse]address\4]
FOR counter = 0 TO 3
HIGH clock_pin ' system clock and I/O clock
PAUSE time
LOW clock_pin
PAUSE time ' system clock and I/O clock
NEXT
HIGH ad
FOR counter = 0 TO 35
HIGH clock_pin ' system clock and I/O clock
PAUSE time
LOW clock_pin ' system clock and I/O clock
PAUSE time
NEXT
HIGH ad
RETURN
get_reading:
LOW ad ' chip select
SHIFTIN serdata_in, clock_pin, 0, [noparse][[/noparse]adc\8]
HIGH ad ' chip select
RETURN
here is a link to the A/D's Data Sheet:
http://focus.ti.com/lit/ds/symlink/tlc541.pdf
I just got my hands on a TLC540IN A/D converter. I am having a little problem interfacing this with my BS2. The data sheet states that the system clock and the in out clock can be tied together to minimize control points. but with this set up i am having a problem writing code for it. I can get the A/D to work but i cannot get the A/D's address to change.
here is a sample of the code i have right now:
sample:
address = 0
LOW ad ' chip select
FOR counter = 0 TO 1
HIGH clock_pin ' system clock and I/O clock
PAUSE time
LOW clock_pin ' system clock and I/O clock
PAUSE time
NEXT
SHIFTOUT address_pin , clock_pin, 0, [noparse][[/noparse]address\4]
FOR counter = 0 TO 3
HIGH clock_pin ' system clock and I/O clock
PAUSE time
LOW clock_pin
PAUSE time ' system clock and I/O clock
NEXT
HIGH ad
FOR counter = 0 TO 35
HIGH clock_pin ' system clock and I/O clock
PAUSE time
LOW clock_pin ' system clock and I/O clock
PAUSE time
NEXT
HIGH ad
RETURN
get_reading:
LOW ad ' chip select
SHIFTIN serdata_in, clock_pin, 0, [noparse][[/noparse]adc\8]
HIGH ad ' chip select
RETURN
here is a link to the A/D's Data Sheet:
http://focus.ti.com/lit/ds/symlink/tlc541.pdf
Comments
Read_ADC:
··LOW CS
· SHIFTOUT·AddrOut, Clock, MSBFIST, [noparse][[/noparse]address\4]
· HIGH CS
· LOW CS
· SHIFTIN DataIn, Clock, MSBPRE, [noparse][[/noparse]adcData]
· HIGH CS
· RETURN·
Note that I wrote this on-the-fly and it's up to you to work out any kinks.
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Jon Williams
Applications Engineer, Parallax
here is the data sheet agian:
focus.ti.com/lit/ds/symlink/tlc541.pdf
Versus...
"The conversion cycle, which requires 36·SYSCLKs, is initiated on the 8th falling edge of I/O CLK after /CS goes low for the Chan. whose Addr. exists in Mem at that time. If /CS is kept low during conversion, I/O CLK must remain low for at least 36 SYSCLKs to allow conversion to be completed."
if it is turned high then low again it would reset the convertion cycle.
Sorry, I don't have one of these on hand.· I thought my quote indicates the /CS (cs) must be active (active low) before starting conversion time.
[noparse][[/noparse] I'll go back and sit in the cheap seats. ]
Post Edited (PJ Allen) : 3/5/2006 12:45:17 AM GMT
1. CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edges
and then a falling edge of SYSTEM CLOCK after a low CS transition, before the low transition is recognized.
This technique is used to protect the device against noise when the device is used in a noisy environment.
The MSB of the previous conversion result automatically appears on DATA OUT.
2. A new positive-logic multiplexer address is shifted in on the first four rising edges of I/O CLOCK. The MSB
of the address is shifted in first. The negative edges of these four I/O clock pulses shift out the second, third,
fourth, and fifth most significant bits of the previous conversion result. The on-chip sample and hold begins
sampling the newly addressed analog input after the fourth falling edge. The sampling operation basically
involves the charging of internal capacitors to the level of the analog input voltage.
3. Three clock cycles are then applied to I/O CLOCK and the sixth, seventh, and eighth conversion bits are
shifted out on the negative edges of these clock cycles.
4. The final eighth clock cycle is applied to I/O CLOCK. The falling edge of this clock cycle completes the
analog sampling process and initiates the hold function. Conversion is then performed during the next 36
system clock cycles. After this final I/O clock cycle, CS must go high or the I/O CLOCK must remain low
for at least 36 system clock cycles to allow for the conversion function.
now because SYS Clock and I/O clock are tied to geather CS can not be set low because i need the clock signal to control the convertion. If it were LOW i would pulse the I/O clock and stop the convertion(The I/O clock is disabled when CS is HIGH). judjing by the statment above this is alowable.
Now by no means was i saying your wrong. I'm too new at this to jump to conclutions. i just read the dada sheet so many times now I almost know it word for word.
thanks for you help
mike