Sx / cpld
BebopALot
Posts: 79
Folks, can the math coprocessor handle SX speeds of 50MHz or greater or is this a situation where a CPLD may be desirable?
Sincerely,
BBAL
Sincerely,
BBAL
Comments
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·1+1=10
Thanks
BBAL
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Chris Savage
Parallax Tech Support
csavage@parallax.com
But all this takes time, actually, now that I think about it here is a good method for on the fly trig functions:
Find a Parallel EEPROM, EPROM or Flash memory. Then write a program to fill it with the nessesary tables for each of your functions, if your argument is 8 bits, you would store tables of 256 entries. Use additional address pins of the memory to specify different tables, say you want sin, cos, tan and atan, then that would take two extra pins (so far for a total of 10), then you need an additional 8 to read the answer back in (up to 22 now). Now you can use latches to reduce the pin count required, but this will introduce additional delays.
But no matter how you slice it you aren't going to have a system that provides an answer 20nS after you supply it with the argument.
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Jon Williams
Applications Engineer, Parallax
<edit> Heck, Jon's code doesn't take much space, you might be able to squeeze it into your primary SX, this would speed up the computation </edit>
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·1+1=10
Post Edited (Paul Baker) : 2/28/2006 9:39:51 PM GMT
Sounds like cool stuff. Any of you guys written a guide or book on it?
In the mean time I'll check out the code.
BBAL
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Jon Williams
Applications Engineer, Parallax
BBAL
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Jon Williams
Applications Engineer, Parallax