Shiftout sclk Inversion

TomS

Is there any way to invert the clock polarity with software when using the SHIFTOUT function? A ~ in front of the cpin doesn't work. All it does is invert the pin number.

Thanks
Tom Smuts

PJAllen

Is it like PULSOUT, where the Pulse is relative to the output state before execution of the instruction (low before gets a HI pulse, high before gets a LO pulse) ?

Paul Baker

I thought you could specify the polarity of the clock by setting it to it's inactive state before calling SHIFTOUT, but I can't verify this in the documents (it may be the behaviour of SX/B's SHIFTOUT). But you should try and see if that does it, (clock is normally high, so try setting it to 0 before doing the SHIFTOUT and see if that reverses the polarity).

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allanlane5

I don't think it should matter. The BS2 implementation of SHIFTIN allows you to clock in the bit just before the Low-High-Low clock pulse (14 uSecs wide) with MSBPRE, or just after with MSBPOST. Since the clock pulse goes LOW-HIGH then HIGH-LOW, you'll have both a positive going edge and a negative going edge -- whichever the polarity the target device is expecting should be triggered.

TomS

Setting the clk pin HIGH before issueing the SHIFTOUT doesn't work. The clock pin is taken low before the first clock pulse per the help file and verified with a logic analyser.

I can do the inversion with an external chip but I want to eliminate it.

Tom Smuts

Bruce Bates

Tom -

If you're looking for a negative-going clock which IS supported on Motorola microprocessors using SPI, there is no way to do that through the software with the PBASIC Stamp. I suppose you could flip the clock pulse externally, if you chose to do so.

Regards,

Bruce Bates

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TomS

Allan,

I'm using SHIFTOUT, not SHIFTIN. You might think is still doesn't matter but it's now dependent of the external device you're writing to. I'm writing to an Analog Devices AD9834 DDS chip and it REQUIRES that the clock be high when the frame sync goes low.

Tracy Allen

I agree with Alan. It usually doesn't matter that the sclk is always set to low before the shift is executed. What are you trying to do that won't work without the inversion?

Set the sclk line low before entering the SHIFT routines. Otherwise you may get an extra negative edge clocking that you don't want when the command starts up. I learned that the hard way when I tried to share the clock line between I2C and SPI devices. I2C likes the clock line to rest high, and SPI (in Stamp flavor of it) likes the clock line to rest low. There are extra steps required to manage the clock line to combine the two. I wouldn't recommend it.

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Tracy Allen
www.emesystems.com

TomS

Tracy,

It doesn't work. If you force the clk HIGH it is brought low before the first clk pulse. TH AD9835 will take this as an extra clk pulse.

Tom

allanlane5

Okay, I've now looked at the data sheet.

It looks like you can do:

HIGH Sclk
LOW Sync
HIGH (or LOW) firstdatabit
LOW Sclk ' Clock·out bit 16 -- Optional, this MAY be what the SHIFTOUT does anyway
SHIFTOUT SData, SClk, MSBFirst, [noparse][[/noparse]RestData\15] ' At 16 Khz, clock in bits 15..1
HIGH Sclk
HIGH SData
HIGH Sync

It may take some experimentation to get some pattern that the DAC will accept -- and it may not be possible at all. But at least this gives you a place to start. The idea is to start the pattern with something that keeps the chip happy, then use SHIFTOUT to send the rest of the bits.

In the worst case you can 'bit-bang' the data, but that's pretty slow...

Post Edited (allanlane5) : 2/24/2006 10:48:41 PM GMT

TomS

Allan,

You may be on to something. I'll give it a try. I do see one possible problem. That is if the data is passed through the DDS chip when clk is LOW and isn't edge triggered. If it simply passes through then SHIFTOUT sets up data before the clk goes high and if the preceding bit was different you would get an error. It's easy enough to try though.

Jon Williams

Hmmm...· it seems that data·is read on the falling edge of the clock so you should be able to use SHIFTOUT without any trickery:

· LOW FSync
· SHIFTOUT SData, SClk, MSBFIRST, [noparse][[/noparse]adcValue\16]
· HIGH FSync

For SHIFTOUT the data is put on the output pin and then the clock pin is blipped 0-1-0, so there is a falling edge while the data bit is valid that your device can use.· Am I missing something?

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Jon Williams
Applications Engineer, Parallax

Post Edited (Jon Williams (Parallax)) : 2/24/2006 11:24:48 PM GMT

CJ

from what I can tell you should be able to use a single NPN transistor and a 4.7k pullup resistor to invert the clock pulse, don't know of any way to do it in software

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Who says you have to have knowledge to use it?

I've killed a fly with my bare mind.

allanlane5

Yes, the issue is that the first bit (the MSB bit, in fact) is supposed to be on the data line, and the clock line sitting high, when the 'Sync' (or chip select ) signal goes low. Thus, when the clock line first drops, that clocks in the first data bit.

So the gyrations above are to implement this, then use the standard SHIFTOUT functionality to shift the rest of the bits. And it should work, since as you say the clock pin is 'blipped' you get both clock edges for follow-on bits.

TomS

I've tried it on with the logic analyser and it looks as if Allan's method will work. Another hour and I'll know if it works in the real world.

TomS

I just tested the DDS chip with the new, improved method. It works.

Thanks
Tom Smuts

TomS

This topic gave me an idea for an enhancement to the Basic Stamp interpeter. How about allowing a modifier, such as a backslash, to the Cpin designator. The backslash would cause the clock to be inverted.

Tom Smuts

allanlane5

Excellent Tom! I'm so glad I could help. It would be kind if you could publish the subroutine that finally worked in the 'projects' area. Many people don't have a logic analyzer, and it sometimes takes that to get just the right set of commands that works for a particular chip.