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Propeller Performance — Parallax Forums

Propeller Performance

william chanwilliam chan Posts: 1,326
edited 2006-03-22 06:02 in Propeller 1
Here are some questions.

1. What are the performance numbers of the propeller chip?
Is it close to 80Mhz x8 = 640 MIPS? Faster than ARM processors? cool.gif

2. Can every processor run at different / it's own clock rate?

3. What is the current consumption at 640 MIPS?

4. Can it be used as the main processor for a child laptop with internet access?

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Comments

  • Ken GraceyKen Gracey Posts: 7,386
    edited 2006-02-24 04:06
    Hi William:

    1. You can't compare it to a single high-MIPS processor by adding them up, because these are parallel. I'd imagine that fewer MIPS/processor is·more when you have multi-processing abilities since more MIPS may be traditionally used (like in the SX) for coding several processes together. However,·running at 80 MHz·each processor is 20 MIPS. If you want to add up MIPS, then you'd have 320 MIPS.·But since you can't get 320 MIPS in a single processor·this additive approach·number isn't·much of an indicator of what Propeller can do [noparse][[/noparse]very fast].

    2. No.·Clock is shared.

    3. At 80 MHz about 75·milliamps.

    4. Perhaps, though you'd likely find a shortage of RAM and perhaps the high-level video objects are of lower resolution than you may desire. But, not having seen a child laptop recently I couldn't say for certain.·The·Hydra game station does·some pretty amazing·Nintendo 80's style games·with a·controller, sound, video and keyboard so it's certainly possible.

    Sincerely,

    Ken Gracey
    Parallax, Inc.

    P.S. Do you want to attend our distributor training seminar at Parallax March 10-11? As an SX distributor this is an option for you.

    Post Edited (Ken Gracey (Parallax)) : 2/24/2006 4:17:07 AM GMT
  • Dave_BellDave_Bell Posts: 11
    edited 2006-02-24 04:58
    Ken Gracey wrote: "However, running at 80 MHz each processor is 20 MIPS. If you want to add up MIPS, then you'd have 320 MIPS."

    Isn't 8*20 MIPS 160, not 320?

    Dave
  • Ken GraceyKen Gracey Posts: 7,386
    edited 2006-02-24 06:38
    Thanks Dave! You are correct.

    I will leave my original post unedited.

    Ken Gracey
    Parallax, Inc.
  • Martin HebelMartin Hebel Posts: 1,239
    edited 2006-02-24 13:01
    Also, when Ken quotes the 75mA, that's with all Cogs running, 80Mhz.

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    Martin Hebel

    Disclaimer: ANY Propeller statements made by me are subject to my inaccurate understanding of my limited time with it!
    Southern Illinois University Carbondale -Electronic Systems Technologies
    Personal Links with plenty of BASIC Stamp info
    and SelmaWare Solutions - StampPlot - Graphical Data Acquisition and Control
  • GadgetmanGadgetman Posts: 2,436
    edited 2006-02-24 13:49
    I wonder how much of that is for each COG, and how much for the PLL/System RAM and other 'hub' circuits.

    And how much it draws on lower speeds.

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  • Martin HebelMartin Hebel Posts: 1,239
    edited 2006-02-24 14:20
    My notes say: 3uA/processor @ 12Mhz

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    Martin Hebel

    Disclaimer: ANY Propeller statements made by me are subject to my inaccurate understanding of my limited time with it!
    Southern Illinois University Carbondale -Electronic Systems Technologies
    Personal Links with plenty of BASIC Stamp info
    and SelmaWare Solutions - StampPlot - Graphical Data Acquisition and Control
  • LoopyBytelooseLoopyByteloose Posts: 12,537
    edited 2006-02-24 14:59
    When you have multi-tasking multi-processing are MIPs really a fair measure of computational speed?
    Is there some kind of synergy that occurs?

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    Post Edited (Kramer) : 3/18/2006 1:25:58 PM GMT
  • Chris SavageChris Savage Parallax Engineering Posts: 14,406
    edited 2006-02-24 15:24
    Kramer said...
    When you have multi-tasking are MIPs really a fair measure of computational speed?
    Is there some kind of synergy that occurs?
    Kramer,

    ·· Multi-Processing...· =)

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    Chris Savage
    Parallax Tech Support
    csavage@parallax.com
  • pjvpjv Posts: 1,903
    edited 2006-02-24 16:46
    Hi Martin;

    The notes I made show the power consumption is 3 uA per COG at 20 KHz.

    Cheers,

    Peter (pjv)
  • william chanwilliam chan Posts: 1,326
    edited 2006-02-25 00:44
    1. Can any processor be shut down or sleep to save current?

    2. Why can't the Propeller do 1 instruction per cycle like the SX? That speed would be really revolutionary !


    Ken,

    Looks like I can't afford the trip to the US this year.
    I am truly sorry.
    The USD 3K++ I need for the trip can buy a lot of Propellers. ( I think )

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  • Paul BakerPaul Baker Posts: 6,351
    edited 2006-02-25 02:23
    The answer is yes to the first question, and I can't answer the second.

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  • GadgetmanGadgetman Posts: 2,436
    edited 2006-02-25 09:00
    Most processors that do one instructions/cycle 'cheats' by having a PLL to multiply the clock...

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  • LoopyBytelooseLoopyByteloose Posts: 12,537
    edited 2006-02-25 13:52
    William,
    To your second question, I suspect the 'pipeline' is the problem.
    Some instructions redirect the program counter and when that happens, the other 3 instructions in the pipeline get dumped.

    In other words, you lose 3 clock cycles waiting for the pipeline to refill.

    I am not sure of the impact here. Either it may cause some jitter [noparse][[/noparse]there is mention of possible jitter in the HUB coding if you try to code for it to arrive precisely at a cog in very tight timing]. Or they may be another source.

    So, no pipeline requires for clocks to go get and so on.

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    ······································································ Warm regards,····· G. Herzog [noparse][[/noparse]·黃鶴 ]·in Taiwan
  • Guenther DaubachGuenther Daubach Posts: 1,321
    edited 2006-02-27 07:07
    There is no pipline in the COGs, IOW, most instruction take 4 clock cycles to be executed.

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    G
  • william chanwilliam chan Posts: 1,326
    edited 2006-03-18 01:27
    Is it better to have a pipeline or not to have a pipeline?

    SX seems to boast of having a pipeline.

    Can anyone tell me why PIC's still cannot run at one cycle per instruction?
    It is due to patent restrictions?

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  • Mike GreenMike Green Posts: 23,101
    edited 2006-03-18 01:45
    A pipeline has advantages (increases effective throughput) and disadvantages (jumps/branches cause the pipeline to flush) like everything else. When there's a lot of strictly linear instruction flow, a pipeline can help. On the other hand, there's a lot of additional circuitry needed to either stop the pipeline when multiple instructions in the pipeline use the same resources (registers and the like) or compensate for that. Often the limitation on how much one can overlap is financial (circuit complexity, die area needed). Throughout the history of computers, there are always bottlenecks whether it's the memory or memory bus or internal processor bus or .... The bottlenecks change every few years and people resurrect old solutions to old problems with new twists. By the way, the "how many cycles does it take to do ...?" question is irrelevant usually. The issue is how fast can you get a function done for a given cost? I'm sure the PICs could be redesigned to do one instruction in one cycle, but at what cost? They're intended to be really cheap and simple. It's usually easier and cheaper to just tweek the chip production process to get more raw speed than to redesign the thing, probably in a much more complicated way, to get the speed.
  • Jon WilliamsJon Williams Posts: 6,491
    edited 2006-03-18 01:46
    This is not the place for a discussion about PIC micros -- that should be taken to another, more appropriate site.· Try www.piclist.com.

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    Jon Williams
    Applications Engineer, Parallax
  • Martin HebelMartin Hebel Posts: 1,239
    edited 2006-03-18 03:09
    Thanks Mike,
    That was really a great discussion on processor design considerations, and since we are all looking at the design of the propeller and considering various issues concerning it, very relevant. I appreciate your insights in this area.

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    Martin Hebel
    Perform an Employer's Survey of Electronic Technologies Graduates· - Click here!
    Personal Links with plenty of BASIC Stamp info
    and SelmaWare Solutions - StampPlot - Graphical Data Acquisition and Control
  • Mike GreenMike Green Posts: 23,101
    edited 2006-03-18 04:01
    As the question was framed, it seems very appropriate. Parallax still sells PIC processors as part of various products and the primary question was about pipelining and performance issues in general.
  • LoopyBytelooseLoopyByteloose Posts: 12,537
    edited 2006-03-18 13:43
    To go back to William's original post,

    1. I think that a 'Child's laptop' of some sort is easily do-able for at least Western languages. In some ways, I think it would be a return to the 8086 days. For a lot of learners today, that would not be a bad thing. Learn more of the concepts rather than rely on brute force and lightning speed.

    2. I suspect that the Internet support is a significant distraction. It really might require a dedicated Propeller that is dedicated to its handling.

    Maybe parents would prefer that such a device didn't intially have the Internet anyway.
    Schools would definitely like a 'no frills' device in the class room. Eliminates wasting time and cheating.

    Toys R' Us nearly declared bankruptcy because kids are less and less interested in toys and primarily playing sophisticated computer games.
    I have a get deal of difficulty with teaching students that spend significant time on gaming.

    A laptop that allows homework to get done -- word processing, spread sheet, data base, calendar, and other such fundamentals would serve education quite nicely.

    The real dilemma is Asian character based languages. You need to use a Unicode character set to include everyone. While the 32bit processing is there, the 7000 plus Chinese characters would require an SD card, a FAT system, and a few other items to call up text. But, you may need the SD card anyway for accumulating data into files.

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    ······································································ Warm regards,····· G. Herzog [noparse][[/noparse]·黃鶴 ]·in Taiwan
  • WaldoDTDWaldoDTD Posts: 142
    edited 2006-03-19 04:18
    Hey,
    Relatively new to the chip scene, cog chips anything to do with MIT's COG project? Also how advanced are we talking here with the chip? I saw it was 32bit and realtime. I just don't want to miss the wave. One suggestion for the logo though how about like a cool looking cyclone/propeller/ninja thing?
  • Beau SchwabeBeau Schwabe Posts: 6,547
    edited 2006-03-19 05:46
    Signol,

    The only thing that could be considered similar is MIT's definition of what COG stands for:
    MIT's FAQ webpage said...

    Q: What does Cog stand for?

    A: It doesn't actually stand for anything. It's a play on the term "cognition" and a mechanical cog. Try finding something that clever in a baby book.

    Reference: groups.csail.mit.edu/lbr/humanoid-robotics-group/cog/faq.html


    Aside from that, I did not find any mention of parallel processing (brief read) although I would not be surprised. The irony is that MIT's COG could
    perhaps benefit with a Propeller or few controlling "some" aspects of their operation.

    Reference: groups.csail.mit.edu/lbr/humanoid-robotics-group/cog/
    groups.csail.mit.edu/lbr/humanoid-robotics-group/cog/current-projects.html



    The Parallax Propeller:http://www.parallax.com/propeller/

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    Beau Schwabe

    IC Layout Engineer
    Parallax, Inc.

    Post Edited (Beau Schwabe (Parallax)) : 3/19/2006 5:49:11 AM GMT
  • GadgetmanGadgetman Posts: 2,436
    edited 2006-03-19 10:39
    Signol said...
    Hey,
    Relatively new to the chip scene, cog chips anything to do with MIT's COG project? Also how advanced are we talking here with the chip? I saw it was 32bit and realtime. I just don't want to miss the wave. One suggestion for the logo though how about like a cool looking cyclone/propeller/ninja thing?

    Pick up your surfboard and start paddling. you're just in time as the wave hasn't arrived yet, but it's coming, and it's a big one.

    No ninja's, please!
    Besides, it's not possible to create a cooler logo than the beanie...
    tongue.gif

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  • LoopyBytelooseLoopyByteloose Posts: 12,537
    edited 2006-03-19 11:18
    Cog = cognition?

    It sounds like we might be creating consciousness.

    I suppose parallel multi-processing is a step closer [noparse][[/noparse]better spontenaity than interrupts]. I have always hated the term 'artifical intelligence' as it seems an oxymoron and an impossible paradox, but 'replicated consciousness' with inherent 'native intelligence' seems feasible.

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    ······································································ Warm regards,····· G. Herzog [noparse][[/noparse]·黃鶴 ]·in Taiwan

    Post Edited (Kramer) : 3/19/2006 3:52:05 PM GMT
  • Beau SchwabeBeau Schwabe Posts: 6,547
    edited 2006-03-19 14:48
    Kramer,

    I was referring more in terms of a "mechanical cog" as in cogwheel/distributor and The use of a Propeller more for exterior
    stand alone functions. Not so much the term cognition referring to intelligence.

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    Beau Schwabe

    IC Layout Engineer
    Parallax, Inc.
  • LoopyBytelooseLoopyByteloose Posts: 12,537
    edited 2006-03-19 16:08
    Acknowledged, MIT doesn't really want to take on cognition either.

    Still, I wonder and dream about how the Propeller might do something very basic and fundamental in that direction. I enjoy robotics because it really does challange us to reflect upon what we are.

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    "When all think alike, no one is thinking very much.' - Walter Lippmann (1889-1974)

    ······································································ Warm regards,····· G. Herzog [noparse][[/noparse]·黃鶴 ]·in Taiwan
  • Chris SavageChris Savage Parallax Engineering Posts: 14,406
    edited 2006-03-20 16:19
    Beau Schwabe (Parallax) said...(trimmed)
    Signol,
    The only thing that could be considered similar is MIT's definition of what COG stands for:
    Or what www.dictionary.com says:

    http://dictionary.reference.com/search?q=cog

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    Chris Savage
    Parallax Tech Support
    csavage@parallax.com
  • FeiFei Posts: 4
    edited 2006-03-21 09:15
    can i ask a question? can the hub serve the processors at random sequence? example 1, 3 5, or 5, 3, 8......
  • GadgetmanGadgetman Posts: 2,436
    edited 2006-03-21 09:38
    No. The HUB serves the cogs in sequence, and at a constant speed.
    Every COG, active or not will be 'serviced' once every 16 clock cycles, and in sequence.

    They could probably have built it to only serve the active COGs, but that would have resulted in a more complex(read: expensive) chip layout and variable timing, which really would mess up the timing when a COG needs to copy more than one LWord of data to or from the HUB memory.

    16clock cycles is enough for 4 assembly instructions, and that is enough for a compact loop. If the HUB suddenly serviced the COG at 12 or 10 cycles, the loop would not match that timing, would 'miss' its slots and be forced to wait for the next time the HUB services that COG. (And suddenly, instead of doing a copy every 16cycles, it does one every 20 or 24 cycles. Not good... )

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  • Bruce BatesBruce Bates Posts: 3,045
    edited 2006-03-21 11:18
    Gadgetman -

    It's curious that it's taken this long for these two GEMS of information to appear:

    "Every COG, active or not will be 'serviced' once every 16 clock cycles ..."

    and

    "16 clock cycles is enough for 4 assembly instructions"

    along with Guenther's earlier, interesting contribution:

    "Most assembler instructions take 4 clock cycles".

    Any other similar tidbits would be greatly appreciated. All along I've said to myself that there were a number of aspects of the Propeller which would lend it becoming a mini-time shared system, and now that thought has spread its wings a bit!

    There is no average or expected ratio of assembler instructions per SPIN instruction, is there? My guess is that there was no attempt to fix such a ratio, otherwise Jeff might have been sent away to a "home" by now smile.gif

    This has given me an entirely new outlook and possible direction on this MOST interesting new chip! Thanks!

    Regards,

    Bruce Bates

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