I/O question

ElectronegativityElectronegativity Posts: 311
edited 2006-02-22 - 20:15:21 in Propeller 1
The discussion of memory in the marathon thread got me thinking about data transfer, and I think this topic is worthy of its own thread.

Using a traditional serial transfer protocol on one line with one 80 MHz processor gives you 80Mb/s
With 8 processors it is obvious that you could extend this to 640 Mb/s, but is it possible to do better?

Having 32 I/O pins seems to open up greater possibilities for parallel data transfer.

With an SX you could the transfer data on 8 parallel lines simultaneously by hooking up each of the pins of a register to one of the data lines and then arranging the data in bytes with everything that will go down line 1 in the first bit, data for line 2 in the second bit etc. By sequentially moving these bytes into an output register you could transmit (or recieve) data at 4 times the clock speed (since the MOV instruction takes 2 clock cycles).

Like my fellows I hunger for more information.

Surely the registry structure is not going to change over the next 2 months.
Maybe we could have just this one teensy morsel? cry.gif

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I wonder if this wire is hot...

Comments

  • SteveWSteveW Posts: 246
    edited 2006-02-22 - 10:12:15
    If you can (without hardware assistance) get a 20MIP micro to do 80-Mbit serial, you're a better man than me...
    Are the video engines suitable for serial out? (and can they do input, too, or just output?)

    Steve
  • Paul BakerPaul Baker Posts: 6,351
    edited 2006-02-22 - 13:59:27
    Something to correct here, the propeller isn't a straight MHz=MIPS like the SX is. The assembly isn't pipelined, so it takes 4 processor clocks to do the simplest instructions (fetch decode execute store). Andre from Nurve LLC has played around with interrelating cogs, if you are good enough in your programming skills it is possible to segregate the processors into two groups of four each group of 4 combining for 1 instruction per clock cycle under very special circumstances, but this is quite advanced so I won't explain the details (it will also be difficult to keep them in this arrangement). Andre has strung all 8 together to make it appear as a single processor (to increase apparent cog program/data space).

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    ·1+1=10

    Post Edited (Paul Baker) : 2/22/2006 2:02:13 PM GMT
  • Kaos KiddKaos Kidd Posts: 614
    edited 2006-02-22 - 14:10:04
    So, in theory Paul, we can have the equevlent of 1 32 bit processor with 16K code, 4096 RAM or 8 indivual processors?
    If I'm understanding you correctly, then with proper codeing we could end up with a number different cog/processor relationships.
    Example:
    (Cog 0)[noparse]:([/noparse]Cog 1)[noparse]:([/noparse]Cog 2)[noparse]:([/noparse]Cog 3)[noparse]:([/noparse]Cog 4)[noparse]:([/noparse]Cog 5)[noparse]:([/noparse]Cog 6)[noparse]:([/noparse]Cog 7)
    OR
    (Cog 0 + Cog 1)[noparse]:([/noparse]Cog 2)[noparse]:([/noparse]Cog 3)[noparse]:([/noparse]Cog 4)[noparse]:([/noparse]Cog 5)[noparse]:([/noparse]Cog 6)[noparse]:([/noparse]Cog 7)
    OR
    (Cog 0 + Cog 1 + Cog 2)[noparse]:([/noparse]Cog 3)[noparse]:([/noparse]Cog 4)[noparse]:([/noparse]Cog 5)[noparse]:([/noparse]Cog 6)[noparse]:([/noparse]Cog 7)
    OR
    (Cog 0 + Cog 1 + Cog 2 +Cog 3)[noparse]:([/noparse]Cog 4 + Cog 5 + Cog 6 + Cog 7)

    Is that the general idea, or is more like...
    1 processor = 8 Cogs
    OR
    8 processors = 8 Cogs

    Man, I'm gettin all kinds of excited about what can be done...
    I can't wait to see the isntruction sets...
    Is there ANY reading I can do to prep myself for this?

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    Just tossing my two bits worth into the bit bucket
    KK
    ·
  • ElectronegativityElectronegativity Posts: 311
    edited 2006-02-22 - 15:34:27
    Thanks for replying guys, but I like the cogs as individual processors.

    What I am trying to get at is the fastest way to get data back and forth between a Propeller chip and external memory.

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    I wonder if this wire is hot...
  • Paul BakerPaul Baker Posts: 6,351
    edited 2006-02-22 - 15:38:40
    The stringing together is not a built in function, plus you will have problems with stringing related code together, say you perform an add on cog 0, and cog 3 wants to do a conditional jump based on if the addition overflowed, cog3 does not have access to the carry bit on cog0 without cog0 placing it somewhere cog3 can read it (cog3 cannot fetch the carry bit from cog0's ALU).

    I probably shouldn't have posted the previous post, it will just serve to confuse people, and without published docs, thats a very bad thing. I was only trying to illustrate that some cogs can under special circumstances work in a collaborative way. So please forget what I said and just wait until the docs are published so you can see exactly what is and isn't possible.

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    ·1+1=10
  • Kaos KiddKaos Kidd Posts: 614
    edited 2006-02-22 - 20:15:21
    Paul...
    No, the comments both help to understand the layout and what we're looking at getting into.
    It's exciting watching all the posts about all the things people come up with on their own.

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    Just tossing my two bits worth into the bit bucket
    KK
    ·
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