Propeller Datasheet
Nate
Posts: 154
I'm not posting a datasheet, I'm asking for one.
Really, this is the most assbackward product launch I have ever seen.· Parallax has developed a new product, but instead of giving out a basic spec sheet we must all play 20 questions?· Looking at that last thread, I could not believe that people are trying to learn the new Spin language or Assembly one command at a time in an entirely random order!·
Why not publish a basic datasheet with what you DO have nailed down, and attach a 'all is subject to change.'· ·If people complain about small changes as the·final product comes out, well, though luck for them.
This sounds like a great product, and if Parallax is smart they will sell it for a ridiculusly low price, establishing a market dominance that no one will ever overcome.·
I actually started this thread to congradulate Parallax, and be the first non-Parallax employee to start a thread in the Propeller forum.· I WIN!!!
Nate·
Really, this is the most assbackward product launch I have ever seen.· Parallax has developed a new product, but instead of giving out a basic spec sheet we must all play 20 questions?· Looking at that last thread, I could not believe that people are trying to learn the new Spin language or Assembly one command at a time in an entirely random order!·
Why not publish a basic datasheet with what you DO have nailed down, and attach a 'all is subject to change.'· ·If people complain about small changes as the·final product comes out, well, though luck for them.
This sounds like a great product, and if Parallax is smart they will sell it for a ridiculusly low price, establishing a market dominance that no one will ever overcome.·
I actually started this thread to congradulate Parallax, and be the first non-Parallax employee to start a thread in the Propeller forum.· I WIN!!!
Nate·
Comments
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Jon Williams
Applications Engineer, Parallax
Chip, Jeff and many other staff at Parallax are working non-stop to ensure all in order for it's very soon release.
Jeff has been good enough to try an answer Q's here, but I'm sure it's really distracting him from getting it done, though I'm sure he's feeling like a proud parent right now.
So, hang loose if you can? I know it's hard, and many of us have waited a long time for something to compete against the stampalikes.
-Martin
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Martin Hebel
Disclaimer: ANY Propeller statements made by me are subject to my inaccurate understanding of my limited time with it!
Southern Illinois University Carbondale -Electronic Systems Technologies
Personal Links with plenty of BASIC Stamp info
and SelmaWare Solutions - StampPlot - Graphical Data Acquisition and Control
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
I wonder if this wire is hot...
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
I wonder if this wire is hot...
So, these two are very busy trying to pull everything together, and you won't be dissapointed.
-Martin
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Martin Hebel
Disclaimer: ANY Propeller statements made by me are subject to my inaccurate understanding of my limited time with it!
Southern Illinois University Carbondale -Electronic Systems Technologies
Personal Links with plenty of BASIC Stamp info
and SelmaWare Solutions - StampPlot - Graphical Data Acquisition and Control
I sure we won't.· Perhaps someday we can tell our children "Yep, I was one of the first to see the Propeller come out - the chip that toppled the market dominance of Intel".....
......then we'll have to run for cover as the autonomus drones of the SkyNet come sweeping over, with their AI systems that run on hoped up Propeller chips, sweeping the earth with a pryrotechnic laser show of death and destruction.....
·
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Jon Williams
Applications Engineer, Parallax
That was just before it decided we were a danger to ourselves and needed 'guidence'······
··· [noparse]:)[/noparse]
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
·1+1=10
Post Edited (Paul Baker) : 2/21/2006 3:49:56 AM GMT
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
--Jeff Martin
· Sr. Software Engineer
· Parallax, Inc.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
"When all think alike, no one is thinking very much.' - Walter Lippmann (1889-1974)
······································································ Warm regards,····· G. Herzog [noparse][[/noparse]·黃鶴 ]·in Taiwan
I'm amazed there is a realm of microcontroller technology where you could spend seven years on the concept and still be at the technology forefront when the product is released.
I'd like to have your crystal ball.
That it has wider instructions that 8bit isn't surprising as many microcontrollers do that, including PICs.
What IS surprising is the width(32bit) and that it allows 'self-modifying code' which means that PROGRAM and DATA spaces must be able to overlap. (Something NOT found on most microcontrollers)
This thing has me more excited than the two weeks I spent waiting for my iBook to arrive...
And almost as excited as while waiting for my Psion S5...
It's probably a good thing that the datasheets aren't available, yet, as I wouldn't be able to get anything done at the office...
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Don't visit my new website...
I've had a great time with the stamps and have recently gotten setup with an SX kit (wow, the potential, too bad I got inebriated one too many times in the ice hut....I'll learn it though).
In the past Parallax has taken shots from people about product teases.· Some people got VERY up in arms about a product that was supposed to be out at 'this' date and wasn't.·
Parallax stopped giving out hints as to what was to come....granted, this is much larger, but I hope everyone keeps it in context and doesn't razz Parallax so much that once again we get our hands slapped.· Of course, one has to expect a little craziness in the hive when a somethings dropped in it, so don't be too mad at us, Parallax, for wanting to know more.·
The can o'worms has been opened!
Look forward to the docs when they're published!
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
·
Steve
"Inside each and every one of us is our one, true authentic swing. Something we was born with. Something that's ours and ours alone. Something that can't be learned... something that's got to be remembered."
I guess I will just have to buy some wide-angle eyeglasses and accept the challenge. At least hexadecimal is more readable.
I keep wondering about those 8 video processor boxes in the COGS.
To date, I haven't really thought much of what a video processor can be, what it looks like, or how to program it. I can only imagine that with 8, you have some sort of animation ability - like having sprites in a video graphics card maybe. [noparse][[/noparse]Again there seems to be another portion of technology that I have been ignoring].
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
"When all think alike, no one is thinking very much.' - Walter Lippmann (1889-1974)
······································································ Warm regards,····· G. Herzog [noparse][[/noparse]·黃鶴 ]·in Taiwan
Gosh, it befoggles the mind what someone with some imagination can dream up with something like this...
I can't wait....
SHMBO has been softly informed,I found myself saying, and I quote myself here, "I will forgo the new 30" tires and 4 inch lift, in exchange for the this...."
She gave me the "dear in the headlights look", "ok dear... if you want... I guess..."
Now all I have to do is wait...
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Just tossing my two bits worth into the bit bucket
KK
·
Speaking of forgo-ing, you don't how much I spent in airlines, hotels and car rentals to be there and be able to get the hardware as a guest [noparse]:)[/noparse]· But it was WELL worth it, if only to see the Parallax gang once again.
-Martin
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Martin Hebel
Disclaimer: ANY Propeller statements made by me are subject to my inaccurate understanding of my limited time with it!
Southern Illinois University Carbondale -Electronic Systems Technologies
Personal Links with plenty of BASIC Stamp info
and SelmaWare Solutions - StampPlot - Graphical Data Acquisition and Control
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
I wonder if this wire is hot...
Is that still available or did Parallax remove it for some reason?
We now have an excellent PDF that prints out as 8 /12 x 11".· Thanks
I started a Video thread if you want to continue posting to that.
There is an SPI thread too.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
"When all think alike, no one is thinking very much.' - Walter Lippmann (1889-1974)
······································································ Warm regards,····· G. Herzog [noparse][[/noparse]·黃鶴 ]·in Taiwan
Post Edited (Kramer) : 2/22/2006 6:45:01 AM GMT
I was wondering about the availability of a datasheet too. I took a look at the block diagram pdf on here. But I couldn't distinguish where on this processor is there an Interrupt pin. I do hope this was just overlooked when preparing the block diagram. I don't see how one can expect to create an embedded design without such a rudimentary but critical function for a processor.
thanks,
Dan
·· There are 32 of them.· This is one of those times when you have to break away from conventional microcontroller designs...Instead of ISR or multi-tasking you have multi-processing, which means concurrent processes...8 of them.· Any one of those can monitor a pin and take action without affecting the others in any way.· Or it can affect the others.· Again, this is something completely different.· Time for a new way of thinking.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Chris Savage
Parallax Tech Support
csavage@parallax.com
Yes, I'm familiar with Multi-processing, as I've designed with this in the past as multi-processors is already a conventional item. From what you're saying, it appears this uses software polling to emulate an Interrupt. You tend to waste precious CPU cycles polling an i/o pin for an event. Although this processor may run faster than the common 8bit MCU's, even the fastest processor justify the need for an interrupt input(even parallel processors). This might be fine if you want to wait for a switch to close. But in the real world an event is always unpredictable. This also factors into whether you can design a real-time system (including Parallel processing). A basic concept in computer architecture, you don't design a processor to wait for an event(ie. software polling an i/o pin), it supposed to react to an event(ie. interrupt the process).
I've seen the pitfalls in some of the biggest companies, namely Motorola and IBM while I was working at Lucent, in designing their new processor chips. Some of the most basic functions such an NMI(let alone some of the more elaborate functions in the Cache) were mishandled on their newest generation processors. One of the important items these companies had was a relationship to garner feedback from their clients during the design phase of a processor chip. I hope this issue is not obscured here and suffers any pitfalls.
thanks,
Dan
Even when using typical interrupts though, it requires clock cycles to place return addresses on the stack, going into the ISR there may be multiple pushes to hold important data before the ISR code is ever executed, not to mention disabling of interrupts during critical main processor code, and having to deal with interrupt priorities or multiple interrupts.
A cog has a hardware-wait which will cease execution until a pin, or a pin configuration, occurs, at which time the code will continue and is immediately executed. Besides tying up a multiple cogs possibly for different interrupt needs, I don't see much of a downside to this new way of approaching this problem.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Martin Hebel
Disclaimer: ANY Propeller statements made by me are subject to my inaccurate understanding of my limited time with it!
Southern Illinois University Carbondale -Electronic Systems Technologies
Personal Links with plenty of BASIC Stamp info
and SelmaWare Solutions - StampPlot - Graphical Data Acquisition and Control
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Chris Savage
Parallax Tech Support
csavage@parallax.com
However, the prelim doc state that the WAITPxx, once the pin pattern is matched, finishes the WAITPxx instruction and executes the next.· This could be imply that there is at a one-cycle·latency (as I seem to recall hearing elsewhere) before the instruction after the WAITPxx.· It could also imply a four or five cycle latency.·
In addition, there is apparently a·5 cycle preparatory period while the WAITPxx configures the COG for the interrupt, but this seems to be part of the period of time that the COG would be in an "interrupt disabled" state, and not thus really part of the question following.·
Assume WAITPNE #0, #000F, meaning (I think)·wait until any of the first eight pins are non-zero.· Regardless of the length of the time from interrupt-to-next-instruction, how can the COG know which of pins were were actually non-zero if the signal duration is less than this time period?· In other words, can an "interrupt" be triggered that leaves the COG senseless of which pins triggered it (I do realise that the "pattern" is known)?
I have in mind mimicing the persistant interrupt mask of some processors, allowing the ISR to poll the combination of interrupts currently active, and manage them, before clearing that mask and returning to its waiting-for-interrupt state.
Daniel
The cpu cycles used for the ISR is typical and is usually effective in how a system would perform in real-time. If you look at existing multi-processor systems, this concept still continues. Way back, I would build a quad Motorola G4 with 2MB of L2 cache in a CPCI system and the software guys would have a heyday trying to make it the cpu load max out.
A Hardware Wait ?, ouch, now I see the Mips performance starting to decrease. This might be fine to dedicate as a coprocessor or slave processor. One thing that you learn in computer architecture is to make sure the cpu is executing as often as possible. Never let a cpu idle, which is why they have pipelines.
A good example of why interrupts are used is communication interfaces. I realize this new processor is a big number cruncher. But eventually you want to connect peripherals to this, besides rs-232, usb, firewire, even wifi in your project. After connecting a slew of peripherals to this (those typically found in bigger MCU's) you tend to be forced to multi-task. I suppose with 8 processors, you can dedicate each cpu to a specific interface. But I find it difficult to propose a parallel RTOS for this, where you usually like to have interrupt events prioritized.
Hey, I'm not trying to play hardball here, but just like to be able to convey some thoughts on what I experienced. I really appreciate the investment you guys are making with this development.
thanks,
Dan
Forget EVERYTHING you know about designing big computers.
The Propeller isn't meant to compete with a G4(at least I don't want the Propeller inside my iBook) or other 'large' CPU.
Ignore the 32bit classification of it, it doesn't matter(except in a few datamove and add/subtracts) and focus on the fact that this is a microcontroller.
It's a microcontroller which can dynamically change its speed from 20KHz to 80MHz, start and shut down any of its 8 cores and can generate 8(! Bl**dy H!) video signals at one time.
In low speed it draws microAmps, but can speed up to 80MHz in moments, whenever something happens, so that it can run almost forever on a small battery-pack. (I was planning to use a BS2P as the brains of a central locking system in my car, but that would mean wasting milliAmps all the time while waiting, and I tend to leave my car alone for weeks... Now I can get down to microAmps, and still get a fast response, have lots of excess processing-power to do all kinds of nifty things...)
If you need to compare it to anything, it would be the CELL processor that Sony is using in their mythical PS3, except that it can't generate video directly, and also, at least 2 of their cores are dedicated, so it's not as flexible.
In fact, forget anything you know about designing ANY computer. Parallax just threw the book out the window...
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Don't visit my new website...
"I'm afraid I can't do that, Dave"
If you want to design a processor, you have to be mindful of the critique.(goes with the territory)
I feel a good application for this would be image recognition. Where each of the processors could be dedicated to a specific function for image analysis. I would interface a OV6620 image sensor(AVR Cam) to this and see how much faster I could get it to track objects. I noticed the thread on FFT, this could also be useful for recognizing images. I'm sure it would offer a significant performance boost.
thanks,
Dan
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
.~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~.
[noparse][[/noparse]My Corner of Cyberspace http://ragooman.home.comcast.net/ ]
[noparse][[/noparse]Pittsburgh Robotics Society Got Robot? http://www.pghrobotics.org/ ]
[noparse][[/noparse]Pittsburgh Vintage Comp.Society http://groups.yahoo.com/group/pghvintagecomp/ ]
.~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~.
I wouldn't look on this as a math processor, in the conventional sense of the word, due to the lack of hardware multply and extensive fast memory resources. But "conventional" is the watchword there. It does have those features Gadgetman mentioned, combined with a very interesting asm instruction set that is well suited to fast integer algorithms. It is first and formost a microcontroller, and I think you are quite right in thinking that it can make a superb peripheral controller for your mainframe (relatively speaking).
Daniel,
It is true the inputs are not latched on this machine. I wonder, the kind of interrupt handling you talk about could (IMHO) to be implemented as a state machine. The minimum pulse width for single events could be one clock cycle plus 4 more to read the input state of the pins, so that would be 12.5 nanoseconds at 80mhz clock and 50 microseconds with a 20 khz clock. In much of the environmental monitoring I do, where the inputs are rain gages and annemometers and keyboards, even 50 microseconds is a lifetime. And 12.5 nanoseconds isn't too shabby. The story would be more difficult with repeating asychronous events, if you are using the WAITpin mechanisms in order to achieve the minimum single event latency. There would be time for propeller to process the state (which would only take a few clock cycles), and then do something with it, like put it in a queue in main memory, and that could eat up quite a few cycles. But let's say the whole process takes 80 clock cycles, including a maximum of 23 for hub rotation. That is still one microsecond overall latency, to define the minimum spacing between asynchronous events with 80 mhz clock, using one cog for the single purpose of "interrupt" queueing.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com
The program sets up 3 loops, 255, 255 and 48, inside each other, then counts them down to 0.
no RET command, no consideration for interrupts or anything, just a paper exercise.
I got this test from someone on a C64 forum, where he wanted to prove the superiority of the 6502 processor over the Z80, so no, the 48 is not my idea...
A Z80 doing this ends up with a program that uses 31.433.108 clock pulses. (about 7.5 seconds run-time at 4MHz)
(After that the C64 user went back to tests of the Basic languages, which I must admit he won... with good margins... )
Writing the same program for a single COG I got this:
MOV $000,#48 LOOP3: MOV $001, #255 LOOP2: MOV $002, #255 LOOP1: DJNZ $002, #LOOP1 DJNZ $001, #LOOP2 DJNZ $000, #LOOP3As I found that the MOV instruction takes 4 cycles, and the DJNZ takes 4 or 8 depending on whether or not it reaches 0, I got these numbers:
(Each line corresponds to the same line of code)
4 4 4 4 48 x 4 192 4 48 x 255 x 4 48.960 4/8 (254x4 + 8) x255x48 12.533.760 4/8 (254x4 + 8) x 48 49.152 4/8 (47x4 + 8) 196Or a total of 12.632.264 clock cycles.
At 20KHz, this takes slightly over 631seconds, or just above 10m31s
At 4MHz, this takes 3.158 seconds...
At 80MHz, this takes 0.157seconds...
Can anyone verify these numbers?
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Don't visit my new website...