EMC failure with SX52 @ 50 MHz

Stolzie

Hi Guys,

I have just had one of my boards tested for EMC and it has failed.

I have done a search and have come across an interesting post in regards to EMC and noticed that there are no other topics about this discussed in the forum. So have any of you guys got your products EMC tested?

As mentioned in the quote below, it is the second harmonics and the rest of them as a matter of fact that is killing me. I have been instructed by the EMC guys to place capacitors on each of the I/O pins of the SX52. I am a little concerned about this idea as wouldn't the capacitance add a certain slew rate to the pins with the charging and discharging of the capacitor? Also I am not to sure what value capacitor to place on the lines or whether there is any other method for killing this EMC problem ( dropping clock speed) but not to sure whether it would work at that speed.

I have tried to do everything right with the design by keeping the tracks as short as possible ( so they don't act as antenna's) but as of what to do now I am unsure.

Any suggestions on this matter or personal experinces would be a great help.

Thanks

Stolzie

G

LoopyByteloose

Gunther firmly believes that the data lines are not the primary source of the problems.

Apparently everything gets reflected, summed up,·and driven through the power lines [noparse][[/noparse]the Vss and Vdd], so he thinks that combination of a 4 layer board [noparse][[/noparse]with Vss and Vdd in the middle layers]·and having all the Vdd lines individually connected to small surface mount capacitors will do most to clean up the problem.

That would avoid having concerns about data lines being affected by slew rate.

I am sorry, but I cannot convienently locate the thread. It is quite long and I believe it occured in the last half of last year.

Just recently the topic came up again [noparse][[/noparse]with Willam Chan] and I think that thread will refer you back. Ignore my tin fold in a sandwich box idea.

Alternatively, reduce your voltage and you will have less output of EMI. The clock rate can stay the same.

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"When all think alike, no one is thinking very much.' - Walter Lippmann (1889-1974)

······································································ Warm regards,····· G. Herzog [noparse][[/noparse]·黃鶴 ]·in Taiwan

Post Edited (Kramer) : 2/3/2006 6:57:38 AM GMT

Guenther Daubach

Stolzie,

please have a look at this thread: http://forums.parallax.com/showthread.php?p=537745. It contains a lot of information concerning EMI problems.

I don't think that placing capacitors on each of the I/O pins will solve the problem. Much more important are bypass capacitors in parallel to the supply pins Vdd and Vss. As you are using the SX52, supply voltage should be fed into all available Vdd and Vss pins with separate filter caps across each pair of Vdd/Vss pins.

Reducing the clock rate alone also does not solve the problem, it only generates different (maybe even more) harmonics. I haver tested a system with 10 MHz clock that generated "nice" harmonics at 20, 30, 40,... up to 200 MHz.

Please have a look at the thread above first. If you have any more questions, I'd be glad helping you (if I can).

BTW: On the boards I had tested, I use SX28s but I think problems are similar with all SX types.

Kramer said:

"I am sorry, but I cannot convienently locate the thread. It is quite long and I believe it occured in the last half of last year."

At the top right of the forum page, you will find a button named "Search". In the search dialog, enter "EMI" as text to be searched, and "last year" in the search period, and you'll find that thread conveniently.

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Greetings from Germany,

G

SteveW

The capacitors to ground on IO pins are a dreadful idea. All that means is that the current pulses to drive the IO to a new level will be even higher. Sure, it'll maybe remove a small amount of the noise when the pin is static, but it's still an abominably bad plan. Resistors are better. Both is best.
First, make damn sure that your power supply is vigorously decoupled. Feed power into the chip (and decouplers) through a surface mount ferrite bead, and make sure that you always put current back where you got it from, to reduce loop sizes. PCB routing is critical. A well-done 4-layer board makes life much easier. On a 2-layer board, you're likely to have to resort to hopping signal tracks around with resistors or wire links, since power and ground (and decouplers) _must_ have priority.
Then, you're on to application specific issues. How fast do you need your pins to switch? How big a load are you driving with each pin? Given these answers, you can stick a series termination resistor at the SX end of each track, to slow down the edges as much as possible while still doing the job that's needed.
If you're driving a load through a resistor already, then always, always, always stick the resistor at the SX end of the trace if there's a choice (and there usually is).
_Then_, you can start sticking tactical capacitors on lines on the non-SX end of the resistors, to knock off even more high frequencies.
However, without knowing anything about your design, layout and software, that's pretty much all the general purpose hints I can offer. Post photos & schematics if you like.

Steve

SteveW

I've just noticed this bit:
"I am a little concerned about this idea as wouldn't the capacitance add a certain slew rate to the pins with the charging and discharging of the capacitor?"

Yes, but slow slew rates are absolutely your friend (up to a point). Slower edges mean fewer, and quieter, harmonics. Unless you're driving DDR2 DRAMs (my current nightmare) or other insanely fast technologies, you really don't want edges anywhere near as fast as the SX is capable of producing. For instance, unless you really care about the phase of a clock (which is pretty rare, on a SX design), then a sine wave is fine, as long as it crosses the necessary thresholds. No harmonics at all... Slow edges, moving as little distance, and as little voltage, as possible, are good.
(The capacitors are still a bad idea, by the way)

Steve

Paul Baker

I am in agreement with Steve, deliberately adding capacitors to signal traces is ussusally best avoided unless you know exactly what you are doing (calculating slew rate, accounting for potential skew etc). In high frequency lines, it is best to shorten the leads (ie route them first). Also rather than adding capacitance it is far more preferable to perform impedance matching of traces ( www.interfacebus.com/Design_Termination.html ) to reduce the reflection (thereby antenuating any standing waves on a trace).

By what Guenther's real-world experiments show, the power plane is a major cause of EMI, and should be addressed.

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SteveW

Note that the power plane isn't the _cause_ of EMI. Taking great care to keep noise off the power supply (by reducing the current drive required from IO pins, reduce the number of transitions, shorten driven traces, reduce loads, blah), decoupling the power with great care as it enters the chip, and all the other good practice things mean that you gain many dB without spending money per board, just at design time. Extra ground and power layers, while almost always a good thing, do cost money. If you don't have the luxury of re-spinning the board a few times to fix issues, and your customer's not too price sensitive, then 4-layer is the winner every time.
Many consumer products, with EMC challenges of the same or worse levels than an SX52, are made on 2-layer boards, but are done exceedingly carefully, and are rarely the designer's first attempt [noparse]:)[/noparse]

Steve

Paul Baker

Sorry, I should have said: Improper design of the power plane can significantly contribute to EMI problems.

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Stolzie

Hi Guys,

Thank you very much for all your replies. It has been a great help.

Thanks for the link Gunther. I searched EMC not EMI hence I didn't find that thread.

My current design does have bypass capacitors to the power supply pins of the SX52 but they are not all individually connected. Two are individually connected while the other two are bypassed by one capacitor. A must fix in the design!

The board is currently a two layer design (with the majority of the bottom layer GND).
Looks as though we may have to update the board design and go with a 4 layer option.

Thanks Paul for the interface design termination link. As I am new to this pcb routing all this information is great.

Thanks steve for all your information too.

Once again I would like to thank all you guys for helping me out with the problem. Thanks, I am off to fix up my PCB and get a new one run.

Best regards

Stolzie

SteveW

If your design isn't super-secret, then post a screenshot before you get it etched - see if we can't save you a spin through the PCB -> EMC cycle.

Steve