Stratix EP1S10 SmartPack programming problem

SimonJH

Hi
Not sure where to post this and I haven't received a reply yet from technical support so I thought I would see if anyone here has any ideas.


We have recently purchased a Stratix EP1S10 SmartPack board and am having trouble programming it. If I build the example project I can program the board via JTAG with no problem.

However, if I use my own VHDL·project, programming always fails with the following "Error: CONF_DONE pin failed to go high in device 1".

I have also tried using the included serial programmer with my·program, but this also fails.

I have created a new single line VHDL project which also fails in the same way. (I am using Quartus II 5.1 by the way). We have made no modifications to the SmartPack board.

Hopefully I have just got a problem with the settgings but I cannot find anything in the documentation.

If anyone has any ideas I would be very grateful.

Thanks a lot

Simon

SteveW

This is really dredging back into the dim & distant past - I've been using Xilinx devices not Altera for a while.
However, it does sound as if you're missing a checkbox (most likely cunningly hidden) called 'drive confdone high' or something. As I recall it, you can either let it float, drive it high, or use it as a GPIO when you're done configuring (although I'm not too sure about the GPIO option - it might be a magical non-reusable pin)
If there's no external pullup resistor, and you don't drive it, then it'll stay low...
However, this is all ancient and dimly remembered, and I've got no idea where you'd find that checkbox in your software.

Steve

SimonJH

Thanks for replying so quickly. I am pretty sure I tried this, but we are also new to Altera. Most of our stuff uses Xilinx.
Whilst I was waiting to see if I received a response from support I had switched back to our Xilinx board but I will double check your suggestion tomorrow.

cheers
Simon

SimonJH

Sad to say I am still having the same problem.

Under Settings->Device->Device & Pin Options...

I have enabled the check box labelled 'Enable INIT_DONE output', but this has had no effect.

I have gone through the example AHDL project to check the settings used there and the above is actually un-checked.

Its bound to be something obvious, but at the moment it has me completely stumped. If anyone has any other suggestions I would be very grateful.

Many thanks
Simon

SteveW

But INIT_DONE isn't CONF_DONE (is it?)....
I suspect there's still a menu you've not found. It could even be somewhere insane like the bitstream generation.
Does Altera's webpage have a help search? Configuring is always the tricky part, so I imagine they'll have documnted it all over the place, and you've got a genuine error message to search for.

Steve

SteveW

By the way, does jtag confirm that the device you've got is exactly the device you compiled for, and it's not just spurning the programming because it's wrong, somehow?
Sorry, these are really random suggestions, but without having the tools here, that's all you're going to get from me [noparse]:)[/noparse]
(I do feel your pain, though - devices that won;t configure are a pain. Have you noticed that the new Xilinx 32-bit parallel configuration mode is bitbackward from the 8-bit version? Thanks, chaps....)

Steve

Ryan Clarke

I have to second SteveW, please verify that you are indicating the correct device and speed-

Ryan

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Ryan Clarke
Parallax Tech Support

RClarke@Parallax.com

SimonJH

Oh Dear

Kicked off by your suggestion in your last posting I think I have just found the problem. I was building the code for a EP1S10F672C6 which is all that is available in the device selection menu.

What is fitted to the board is a EP1S10F672C6ES, the important part is the ES on the end which denotes 'Engineering Sample' as far as I understand it that also equates to 'Free of charge'!.

That is enough to make you feel a little cheated, however the important part is that it does not seem to be possible to select this device in the selection menu. The only way I have got around it is to open the Parallax example project then create a new project but press the 'Use same settings' button.

This created a project for the Engineering Sample device and allowed me to successfully program the part. However, when I changed back to the original part to check that programming still failed the 'ES' device disappears from the selection menu again...

There must be a way to install support for this part into Quartus and I think I will email technical support again to see if they can advise me on how to achieve this.

In the mean time, many thanks for your suggestions. Got there in the end.

Cheers
Simon

SteveW

I'm not yet convinced. I think that, when you created the project, copying the settings, you brought across something other than the device code. I still think there's something, somehwere, you're not setting, when you create a project from scratch.
If ES does stand for engineering sample in this case, I wouldn't expect it to behave any differently from real silicon, certainly not at a level that would make is fail programming.
I'm prepared to be wrong, naturally, but I don't think you've found the root cause yet. (However, if you _can_ work inside a template project based on the supplied demo, you'll be able to get on with development while you find the real answer...)

Steve

SimonJH

I feel reasonably confident, as when I created the template project I could program the board. However, when I changed the device selected to the non-ES device (but left the rest of the project the same) I got the same programming error.

Also if you 'Auto detect' the device in the Quartus programmer it detects it as a EP1S10-ES, although this does not appear in the device list as far as I can see. When you attempt to load a file the device changes to that selected in the project menu.

As you say, I could well be kidding myself. I would much prefer to start a project from scratch and have it work.

Least I can get started now anyway.

cheers
Simon

SteveW

Fair enough - now I'm convinced [noparse]:)[/noparse]
Very odd for ES status to be represented in the jtag ID, but there you go. Yay!

Steve

SimonJH

Just for information, in the unlikely event that anybody else has this problem!

The Stratix FPGA Family Errata Sheet details the reasons why the EP1S10 device configuration files cannot be used for the EP1S10ES device.

Also the EP1S10ES device is hidden in the 5.1 version of Quartus software, but the following from Altera explains how to get it to work...

<snip>

Actually QuartusII 5.1 still supports EP1SF672C6ES device but it is hidden and you can not see it in the devices list because Altera will not recommend customers to use this old device in their new products. If you do want to target to it, you can firstly select EP1SF780C6ES as the target device, open the .qsf file, modify EP1SF780C6ES to EP1S10F672C6ES, then save the .qsf file and compile the project again. This will be a workaround for you.

<snip>

For example, this is how the line in the qsf file should end up...

set_global_assignment -name DEVICE EP1S10F672C6ES

Hope this helps someone else, as its wasted a couple of days for me!

cheers
Simon