ISR Skipping
Javalin
Posts: 892
All,
Happy new year again!
Why would an ISR be skipped at RTCC roleover?
I.e. running for a UART VP every so-often the ISR will not fire at a RTCC $FF roleover even though RTCC roleover is enabled and there is a 1:1 pre-scaler?
Seems to happen when the RTCC is put back by the usual mov w,#-int_period and RETIW instructions, to a high ($A0 ish)·value.
Im using an SX18 at 50mhz with the following DEVICE directive:
DEVICE·SX18,OSCHS3,TURBO,STACKX,OPTIONX
I've checked with SX-SIM and I dont believe my code is overflowing the ISR (int_period is 108)
Cheers
james
Happy new year again!
Why would an ISR be skipped at RTCC roleover?
I.e. running for a UART VP every so-often the ISR will not fire at a RTCC $FF roleover even though RTCC roleover is enabled and there is a 1:1 pre-scaler?
Seems to happen when the RTCC is put back by the usual mov w,#-int_period and RETIW instructions, to a high ($A0 ish)·value.
Im using an SX18 at 50mhz with the following DEVICE directive:
DEVICE·SX18,OSCHS3,TURBO,STACKX,OPTIONX
I've checked with SX-SIM and I dont believe my code is overflowing the ISR (int_period is 108)
Cheers
james
Comments
You may already know this, but if using the debugger sometimes you will see the ISR, and sometimes you won't.· The only way to use the debugger to test for ISR performance is to put a breakpoint in the ISR.
When I get this problem, and I am detecting the ISR entrance by some signal generated within the ISR, the problem has always been in my signal generation logic.· Make sure the ISR is not using any variables that are used by the main program unles you mean to do this.· Also make sure the ISR doesn't alter any banks (FSR) that the main program doesn't know about.· Finally, make sure the main program is not changing the RTCC counter.
Nate
Thanks for the reply!!
Yes its via the debugger you can see the roleover and the "skip" of the ISR
The Bank is changed by the ISR - but I thought the ISR saved and restored the PC, FSR, W, etc?
James
Post Edited (Javalin) : 1/2/2006 7:34:01 PM GMT
My point is that when debugging, watching for the ISR to be executed is a pointless task - the operation of the debugger conflicts with the operation of the ISR.· Rest assured, when running in normal mode (ie not debugging) the ISR always happens on RTCC rollover (or multiple thereof, if prescaler enabled).
You are also correct that W, Status, PC, and FSR (and M, SX48/52) are saved via the shadow registers, my mistake.· I will reiterate however, be careful what you do in the ISR - I can't count the times that I have spent trying to understand odd results of a program, only to find out the unexpected results are due to my own ISR that I forgot to take into account!
Nate
Post Edited (Nate) : 1/3/2006 3:50:03 AM GMT