Shop OBEX P1 Docs P2 Docs Learn Events
THIN Q package? — Parallax Forums

THIN Q package?

Beau SchwabeBeau Schwabe Posts: 6,568
edited 2005-12-23 15:54 in General Discussion
Anyone ever used a "Thin Q" package?

I just ordered a few sample IC's from Maxim for something I want
to try and that's the only size they had available in their free samples.

MAX5481ETE & MAX5494ETE

I can't seem to get a decent package description other than it is
a 5mm square with 4-pins on a side for a total of 16 pins.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Beau Schwabe

IC Layout Engineer
Parallax, Inc.

Comments

  • Paul K.Paul K. Posts: 150
    edited 2005-12-23 02:05
    Beau,

    Had some time to kill at work and couldnt find anything clearer than this.

    Both Package codes are on here its just figuring out everything. pdfserv.maxim-ic.com/package_dwgs/21-0136F.PDF


    Paul

    Post Edited (The-electronics-guy) : 12/23/2005 5:36:30 AM GMT
  • Paul BakerPaul Baker Posts: 6,351
    edited 2005-12-23 13:54
    I have not used it yet for a good reason, the package is designed for reflowing, the underside of the chip is a ground plate that is supposed to be soldered onto a corresponding exposed copper pad in the center of the land pattern. Clearly this is a difficult thing to do without a method of reflowing. I have contemplated doing a special design of the center pad. The idea is to use a ring of vias around the perimeter to tie the pad to the underside ground plane, then in the center of the pad, have vias that are not connected to anything else, then soldering the pad would consist of placing the iron on center vias until the paste on the pad reflowed. I dont know if it will work, I haven't tried. It may be nessesary to reduce the number of vias to the ground plane in order to reduce the thermal conductivity between the pad and ground plane. Here's an example diagram, the blue is the ground vias, the red are the heating vias.


    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    ·1+1=10
    261 x 228 - 8K
  • Dave PatonDave Paton Posts: 285
    edited 2005-12-23 14:41
    Paul Baker said...
    I have not used it yet for a good reason, the package is designed for reflowing, the underside of the chip is a ground plate that is supposed to be soldered onto a corresponding exposed copper pad in the center of the land pattern. Clearly this is a difficult thing to do without a method of reflowing. I have contemplated doing a special design of the center pad. The idea is to use a ring of vias around the perimeter to tie the pad to the underside ground plane, then in the center of the pad, have vias that are not connected to anything else, then soldering the pad would consist of placing the iron on center vias until the paste on the pad reflowed. I dont know if it will work, I haven't tried. It may be nessesary to reduce the number of vias to the ground plane in order to reduce the thermal conductivity between the pad and ground plane. Here's an example diagram, the blue is the ground vias, the red are the heating vias.
    Paul-
    I've done just that, after a fashion. I generally use a hot air gun (the soldering version of a hairdryer..Weller makes a great one) to preheat the board and the chip. For a Tripath board I did, I flowed about 3/4" of Kester 63/37 onto the heat slug on the board, and then placed the chip over it. With the heat gun on the bottom, occasionally alternating to the top, it took about 45 seconds to get the solder to reflow under the chip and sung it down nice and tight to the board. I liberally covered both the bottom of the package and the board slug with flux from a KEster flux pen before I started, and I think it helped a lot. I'd really prefer to do it in a batch oven, but I don't have one here at work any more, so I MacGuyver what I can. smilewinkgrin.gif

    It mostly works, but I never do it on one-of-a-kind things, because I have killed a few chips before. Not often, but once and a while.

    -dave

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    This is not a sig. This is a duck. Quack.
  • Beau SchwabeBeau Schwabe Posts: 6,568
    edited 2005-12-23 14:57
    Thanks Paul (The-electronics-guy) , Paul Baker, and Dave!

    Paul Baker,

    Since this is a test circuit (wide range VCO application), and the IC's are
    freebee’s, I was thinking about flipping the chip upside-down and connecting
    it (bond wire fashion) to something more manageable like a DIP package for
    testing purposes.

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    Beau Schwabe

    IC Layout Engineer
    Parallax, Inc.
  • John R.John R. Posts: 1,376
    edited 2005-12-23 15:02
    Taken from another thread:

    ······ Don't forget a penny for a heat sink!

    (You might have to trim it down, but I promise not to call the T-men.)

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    John R.

    8 + 8 = 10
  • mmmm Posts: 56
    edited 2005-12-23 15:20
    oh yes the QFN package, quad flat pack no leads, or the DFN, dual flat pack no leads, the DFN is 2mm by 2mm. I Just got a bunch of Switched cap boost converters for a wireless ear mic application and they were either QFN or DFN packages. I was able to do the first DFN by hand using one of my assemblers smallest SMT tipped irons but not the QFN pkg and the 2nd DFN I couldn't get soldered. I finally had a smt protoboard made up and used a hot plate to solder the QFN and DFN's n my lab.

    The unfortunate thing is that most of the newer really nice SMT parts are only available in these leadless sizes and not the more useable SO-IC pkg but hey try to make a wireless ear mic in any older SO pkg and see how much the users ear droops. At least they aren't of the BGA style packages now these are impossible even with a solder plate.


    Mike
  • Paul BakerPaul Baker Posts: 6,351
    edited 2005-12-23 15:27
    I can't wait until they perfect ECA (electrically conductive adhesive), once that happens alot of the difficult packages will be much easier to work with by an ordinary hobbist.

    Dedbugging the chip would work for prototyping, though you may have to account for lead inductance if the VCO frequency you are working with·is high enough.

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    ·1+1=10

    Post Edited (Paul Baker) : 12/23/2005 3:30:02 PM GMT
  • Beau SchwabeBeau Schwabe Posts: 6,568
    edited 2005-12-23 15:54
    Paul,

    I understand what you are saying, but I don't think that the lead inductance will be so much as
    a problem as parasitic resistance. The "digital pot" is NOT in the oscillator loop, and strictly
    provides a voltage reference. By combining 3 "digital pots" with 10-Bit resolution in a particular
    arrangement I can get a 20-Bit resolution output. Frequency "drift" from temperature is not too
    much of a concern as long as the overall temperature is stable. The design will be able to
    self-calibrate by reading back the actual frequency at specific known "digital pot" intervals.

    Eventually I hope this project will move into the "Projects" folder, as I think it might be a valuable
    testing tool for the hobbyist.

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    Beau Schwabe

    IC Layout Engineer
    Parallax, Inc.
Sign In or Register to comment.