RTCC and the instruction clock
SXUser
Posts: 4
Hi Guys !
I'm a new member but with some experience with ucontrollers. Does anyone know for sure if the RTCC edge select bits (in the OPTION register) have any effect on the RTCC when driven by the·INTERNAL instruction clock ? I want to drive the SX with an an external clock source and setup the RTCC so it increments on each internal intruction cycle. Is the external clock signal fed directly to the RTCC or is there phase inversion or some delay ? Can I select which edge of the internal instruction clock the RTCC detects ? Any comments/ideas/thoughts will be greatly appreciated. Thanks in advance.
I'm a new member but with some experience with ucontrollers. Does anyone know for sure if the RTCC edge select bits (in the OPTION register) have any effect on the RTCC when driven by the·INTERNAL instruction clock ? I want to drive the SX with an an external clock source and setup the RTCC so it increments on each internal intruction cycle. Is the external clock signal fed directly to the RTCC or is there phase inversion or some delay ? Can I select which edge of the internal instruction clock the RTCC detects ? Any comments/ideas/thoughts will be greatly appreciated. Thanks in advance.
Comments
Other options are to provide a pulse directly to the RTCC which is counted according to software decisions and then does a roll over to interrupt the main program and divert to an interrupt service routine [noparse][[/noparse]a specialized subroutine] at a rate less than the actual clock
or
establish an interrupt via any, some or all of the Port B pins which will divert to an interrupt service routine which again is less than the actual clock.
Read section 1.9 of Gunther's text.
The RTCC pin is not a true external oscillator port. It is an interrupt/counter. Nonetheless, it is useful. For example, it can count pulses and the total can be compared againts another timer tied to the Osc to determine an actual pulse rate or frequency rate.
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"When all think alike, no one is thinking very much.' - Walter Lippmann (1889-1974)
······································································ Warm regards,····· G. Herzog [noparse][[/noparse]·黃鶴 ]·in Taiwan
Thanks for your help but my question has not been answered. What i want to know is: When the SX OSC input pin is driven externally and the RTCC is driven internally (by the instruction clock), do the RTCC edge select bits in the OPTION register have any effect or are they ignored ?
From the literature it seems that you can clock the SX-Ubicoms nearly down to zero and still have function as long as you provide adequate and stable power supply.· The software just runs at the rate the osillator is functioning at.
I suppose the only real question comes into play when the oscillator is not regular [noparse][[/noparse]if the rate is flucuating between fast and slow].· I suspect that even that might work if the duty cycle is roughly near 50/50.
I don't think stopping the oscillator is a good idea, but someone else would have to tell me why.· It is just a hunch.· If you could do it, you might be able to suspend the i/o ports in their various states indefinitely.
The real challange is to deterministically program the changes in the timing.·
Can you do that? Or do you even want to?
Sorry that I cannot offer more than mere speculation.· Maybe someone that has been there, done that will jump in.
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"When all think alike, no one is thinking very much.' - Walter Lippmann (1889-1974)
······································································ Warm regards,····· G. Herzog [noparse][[/noparse]·黃鶴 ]·in Taiwan
What are you trying to do that you need the RTCC to increment on a specific phase of the input clock? How critical is this application you are planning?
Thanks, PeterM
In reply to PeterM : I want to use the SX to control a fast synchronous dual port SRAM chip and in the circuitry the read/write clocks are 180 deg out of phase. Since im using one clock source for the whole board i would like to have precise control of the read/write sequence. Seeing that you understand my question - please tell me what is your answer ? Has this been discussed before ? Does anyone at Parallax,Ubicom,SCENIX or Earth actually know ? Please help - we all can benefit from this kind technical information which is NOT given in the datasheet. Thanks guys.
If you're controlling the SRAM, doesn't that mean that you just need to generate a pair of clocks that are 180 out of phase? In other words, if you are generating the clocks, then who cares what the RTCC is doing? If all you want to do is create a symmetrical clock, you can do that by simply writing the correct byte values to any port. Since the port updates all the pins simultaneously, sending it a value of 1 followed by a value of 2 and repeating will cause bits 0 and 1 to toggle 180 out of phase with each other.
If I am missing something here, then let me know. Also, what specific SRAM are you controlling?
Thanks, PeterM
However, if you are driving the SX cpu with an external clock, there is nothing to stop you from connecting the incomming clock to both the OSCIN and RTCC pins, which would allow you to change the RTCC clock phase.
The problem that I hane with your question is it ignores the fact that the SX cpu is not affected in any way by which clock edge that you use.
The SX series of processors execute instruction at the rate of one instruction per clock cycle.
Whether you use the RTCC as a readable register or to generate an interrupt, the CPU will always read/respond to the value as synchronized to the CPU clock on that cycle.
The datasheet does not specify the point in a cycle at which, for example, an input pin is sampled, but you can assume that it will be consistant.
The following code samples assume that the cpu clock is connected to Port B pin 0:
LOOPHIGH:
sb portb.0 ; Test the pin, skip if pin high
jmp LOOPHIGH ; repeat until the pin is high
LOOPLOW:
snb portb.0 ; Test the pin, skip if pin low
jmp LOOPLOW ; repeat until the pin is low
Even though the pin is continiously toggling, one of these loops will always drop through immediately, and the other will loop forever.
If you invert the phase of the CPU clock as connected to the input pin, the only thing that will change is which loop drops through and which loops for ever.
Assuming that you are trying to clock the SX cpu is sync with the SDRAM and then generate the RD, WR etc. control signals in s/w on the SX cpu, I suggest that you clock the SDRAM at half the CPU clock. You could do this with an external FlipFlop, or (if you use the SX48/52) with one of the counter/timers.
Assuming, for the following example, that the SDRAM clock is connected to Port B pin 0, and you want to drive RD low (Port B pin 1) on one phase of the SDRAM clock and WR low (Port B pin 2) on the next phase:
SDRAMCLKLOW:
nop
snb portb.0 ; Test the pin, skip if pin low
jmp LOOPLOW ; repeat until the pin is low
clrb portb.1 ; drive RD low
clrb portb.2 ; drive WR low
If the SDRAM clock on Port B pin 0 is low when the CPU executes the SNB instruction, the skip will be executed (taking 2 CPU clocks, 1 SDRAM clock), then the RD pin will go low followed by the WR pin one CPU clock later. Since one CPU clock equals one half SDRAM clock, WR changes on the opposite SDRAM clock phase to RD.
If the SDRAM clock on Port B pin 0 is high when the CPU executes the SNB instruction, the skip will not be executed (1 CPU clock) so the jump will be taken (3 CPU clocks) followed by the NOP (1 CPU clock). Now the skip test will be repeated. Since we have executed 5 CPU since the previous test, the SDRAM clock should now be on the opposite phase and therefore the skip test will be true and the skip will be taken.
I hope this helps you with your project. When interfacing the SX CPU with high speed hardware, it is often important to count the number of CPU clocks between each change in an external signal.
The SX datasheet does not indicate the delay between an I/O instruction (eg clrb portb.1) and the actual change of the pin. To make my sample code work as you wish you may need to use a scope or logic analyser to fine tune the code. Since you cannot control the cpu clock to output time, it may be impossible to meet the setup and hold times required for your SDRAM without further dividing the SDRAM clock.
Regards, Hugh
Note that the nop is important.