Auto reset
Peter Verkaik
Posts: 3,956
Hi,
In the attached schematic is an auto reset circuitry.
The idea is to let an SX28 I/O pin reset both a stamp and the SX28.
What I would like to know:
is there a minimal hold time for the stamp reset input?
is the C1 cap necessary to create this hold time?
is the R2 value too large? R2 protects the SX28 I/O pin.
When the SX28 I/O gets a low output, the reset line will go low (discharge C1)
but then the SX28 resets, so the SX28 I/O pin will revert to an input (charge C1)
Comments please.
regards peter
In the attached schematic is an auto reset circuitry.
The idea is to let an SX28 I/O pin reset both a stamp and the SX28.
What I would like to know:
is there a minimal hold time for the stamp reset input?
is the C1 cap necessary to create this hold time?
is the R2 value too large? R2 protects the SX28 I/O pin.
When the SX28 I/O gets a low output, the reset line will go low (discharge C1)
but then the SX28 resets, so the SX28 I/O pin will revert to an input (charge C1)
Comments please.
regards peter
pdf
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Comments
this is an interesting circuit to do an auto-reset. I never did domething like this so far, therefore, I can't tell if it can generate a "clean" reset. As you had mentioned, when the SX I/O pin goes low, controlled by the SX application, it will pull low the reset line, so the SX will perform a reset which makes the I/O pin go high-Z. So, most likely, the SX will reset. The question is if this relatively short high-low-high transition on the reset line is long enough to reset the BS. Actually, "low" does not mean 0 V - it is the remaining voltage across the capacitor that is just below the SX /MCLR low threshold level. The datasheet specifies this value as 0.2Vdd.
For auto-resetting an SX, I use another "trick": I activate the watchdog timer, and make sure that a clr !WDT is executed often enough in the "regular" pogram loops. When I want to do an auto-reset, I bring program execution into an endless loop where the watchdog timer is no longer cleared. This causes a reset as soon as the watchdog timer conter overflows. You could extend this to reset the BS by connecting one SX I/O pin to the BS reset line. At startup of the SX program, you then pull this pin low, long enough to safely reset the BS.
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Greetings from Germany,
G
I didn't think of the wdt.
Then I only need to connect the reset button·to the SX28 MCLR input.
The SX28 I/O pin will connect to the stamp reset pin, no cap needed.
The SX28 status register allows me to distinguish between a powerup/mclr reset
and a wdt reset, so I could count the number of wdt resets during which
no communication is estabished between the SX28 and the stamp·and if that
number exceeds a certain value, I could signal a buzzer, indicating hardware
failure (one stamp pin also connects to that buzzer in case the SX28 fails).
regards peter