Edge Detection and Interrupts

RonW

I need to detect transitions on RB7 and RB6.

I need to syncronize the RTCC to the falling edge of RB.7, so RB.7 transitions are set to cause an interrupt. The ISR clears the WKPND_B register.

RB.6 is a short input pulse, but response time is not critical, so RB.6 is checked in the main loop using:

Temp = 0
WKPND_B = Temp
IF Temp.6 = 1
PulseDetected = 1
ENDIF

Here's my question: Am I guaranteed that every falling edge on RB.7 will cause an interrupt and that the ISR will always see WKPND_B bit 7 set?

My concern is that if a transition occurs on RB.7 just before the main loop writes to WKPND_B, then WKPND_B bit 7 may be cleared before the interrupt is initiated. Not only does the interrupt need to occur, but the ISR needs to be able to read that WKPND_B bit 7 is set. If it works as I hope, the main loop woud never read a 1 in WKPND_B bit 7 as long as the interrupt is enabled.

Incidently, I realize that the ISR is also clearing WKPND_B bit 6 and I've handled that.

Thanks for your help.

RonW

Paul Baker

Ok first off, mixing async (edge detect) and sync (RTCC) interrupts, does cause problems, because the SX does register interrupts while processing another interrupt, but does not call the ISR again, so you must explicitly check. Second, messing with the WKPND_B is typically only done in the ISR.

It appears that you are attempting to synchronize the RTCC with an external device. Recently some code was share on how to do this without using the edge detect interrupt, I believe it was Peter (pjv) that shared it with us. I will look for it and post the link to the thread when I find it.

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Paul Baker

Here you go: http://forums.parallax.com/showthread.php?p=550794
it started off as a discussion of matching resonators, when it became more clear what the aim was, Peter gave the algorithm on how to do it on the second page towards the top. Hope this helps.

Man I love the new search engine, just searched "forums.parallax.com pjv synchronize" and bam the very first hit .

Oh and he has master and slave code in his last post.

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Post Edited (Paul Baker) : 11/11/2005 7:51:47 PM GMT

RonW

Paul,

Thanks for the help. I'm not actually using async and sync interrupts at the same time. Once I've sync'ed with the edge, I turn the edge interrupt off and turn the RTCC interrupt on. When the input goes idle, I switch back to edge detection to sync with the next incoming pulse train. This is working fine.

Thanks for the reference to the other thread. Since I don't have any control over the input, I can't implement that syncronizing scheme in this project, but it's good information. My rates are slow enough that I could use periodic polling if necessary.

There are other ways to accomplish what I need, but if I could count on not missing an interrupt, this solution is very simple.

Thanks,
RonW

Paul Baker

I would shadow copy the WKPND register for handling RB.6. This would be done by handling the WKPND (for both RB.6 and RB.7) in the ISR, copy the value into another register, test for RB.7 and handle it in the ISR. Then in your main code it would check the RB.6 WKPND bit via the shadow register. If you want to be sure an RB.6 event isn't missed (Via a subsequent RB.7 interrupt), OR the WKPND with the shadow register, that way the ISR can set the RB.6 but cannot clear it. Then your mainline code will clear the register upon checking it.

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