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Early transistor/relay computers — Parallax Forums

Early transistor/relay computers

Armored CarsArmored Cars Posts: 172
edited 2005-11-11 17:37 in General Discussion
I want to build a very very simple transistor computer but need some way to remember a single bit even when powered down.

Comments

  • Chris SavageChris Savage Parallax Engineering Posts: 14,406
    edited 2005-11-08 18:53
    Latching Relay?

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    Chris Savage
    Parallax Tech Support
    csavage@parallax.com
  • Jon WilliamsJon Williams Posts: 6,491
    edited 2005-11-08 18:58
    Magnetic core memory?

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    Jon Williams
    Applications Engineer, Parallax
  • Clock LoopClock Loop Posts: 2,069
    edited 2005-11-08 20:40
    Rubber bands? Uhh,,,,
  • Armored CarsArmored Cars Posts: 172
    edited 2005-11-08 21:07
    Not much available on magnetic core, but latching will work for what I need.
    I also spent awhile (too long) looking for mercury delay tubes until I realized they had mercury in them and are probably outdated anyways. So far I havn't been able to find anything to use in place of them. I need something to delay current through a wire about one tenth of a second. Couldn't find any slow acting relays; a charging a large capacitor might also work, though I don't know how to figure the size or delay time. Havn't been able to turn up anything on Google yet.
  • Paul BakerPaul Baker Posts: 6,351
    edited 2005-11-08 21:30
    I can give you some pointers on delay lines, but they are not non-volatile (as your first post's criteria indicates)

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  • Armored CarsArmored Cars Posts: 172
    edited 2005-11-08 22:17
    That would be great!· The delay lines are not related to my first post, the latch relays will work for that.· It was just another problem I ran into that I threw into this post because it was somewhat related.· I should probably be more specific more often.






    Do what I mean, not what I say! smile.gif
  • Paul BakerPaul Baker Posts: 6,351
    edited 2005-11-08 23:01
    Do you have a system clock, or will it be an asynchronous computer?

    PS be patient, as Im about to leave work, and I do not have internet at home at present (gotta pay the bill, wont have the money until Monday to do so).

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  • Armored CarsArmored Cars Posts: 172
    edited 2005-11-08 23:06
    For what I am doing now, no clock.
  • RickBRickB Posts: 395
    edited 2005-11-09 06:41
    I have a couple of magnetostrictive delay line modules. About 20" x 20" x 2". Arranged in multiple spiral layers with transducers at ea end, but no electronics. Don't know what the delay is. Would have to find and unpack them. These were used as serially accessible memory. Designing the electronics would be a "fun" task. I would consider selling 1.

    Rick

    Post Edited (RickB) : 11/9/2005 3:35:10 PM GMT
  • Armored CarsArmored Cars Posts: 172
    edited 2005-11-09 14:26
    I need lots of something equivilent to a mercury delay tube. It takes 2 per bit and I need 10 bits for this project.
  • Paul BakerPaul Baker Posts: 6,351
    edited 2005-11-09 15:59
    Armored Cars said...
    For what I am doing now, no clock.
    I was afraid you were going to say that, before I get into how to make asynchronous delay lines (because all commercially availible async delay lines are measured in nanoseconds and not milliseconds), Id like to explain something you may not be aware of about asynchronous computing.

    Since the invention of the transistor, asynchronous computers have been considered a very advanced subject. Until 6 months ago, the only asynchronous computers commercially availible (that I am aware of) were bit-slice computers, or single bit computers. The reason for this is very simple: propagation delay. Because of process variation, each gate's propagation delay will be slightly off, mainly from variations in channel width and parasitic capacitance, added to this is variations in signal line width (caused by process) and length (caused by design). When adding all these variations up on a multibit computer, signal skew will occur, this is when one bit arrives at the next stage sooner or slower than the other bits, the more bits, the more skew. A system clock creates a wait station by introducing a register which clocks all bits in when it is known that all signals have arrived, this resyncs the bits to one another. When designing an async computer out of discrete transistors or discrete gates, the variation of skew is amplified.

    Now that you have been alerted to the pitfalls of asynchronous design, if you decide to stick with this approach, Ill help you design an asynchrounous delay line, but it is roughly 10x more complicated than a synchronous delay line, and requires considerable parameterization, calculation, experimentation and fine-tuning, because to get a precise device, you must know the particular behavior of each delay line which can only be determined after it is built, and each ones' behavior will be slightly different, requiring individual compensation.

    To give you a window into the proposed method it will consist of one or more stages of buffers and fine tuned capacitors. There are other more esoteric methods, but because they are esoteric, they are very expensive, mercury delay lines have not been used really since the very first computers.

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  • Armored CarsArmored Cars Posts: 172
    edited 2005-11-10 04:27
    Maybe I'm using the term computer too loosely.
    What got me started was I needed a way to switch some speakers in my car. I could have used a toggle switch, but I had a push button that looked really awesome and wanted to use that. My first thought was to use an SX to debounce the button and switch the relays, but as I got thinking about it I realized I could do the whole thing with relays.

    The pic is what I came up with. Hopefully you can follow my perfectly correct schematic.
    Basically the power from the pushbutton goes straight through relay 1 and toggles relay 2. Relay 2 constantly has current flowing through it and will toggle relay 1 after a short delay, which, according to the plan, is after the push button is relased. This delay is where I get hung up, which is what I origionally decided to come here for.
    Here I need no clock. If making a delay without a clock is too complicated, I'll probably just use an SX.

    Back to my origional problem, the toggle circuit for my car. I realized that if I lined a bunch of these up I could count in binary, and then, using AND and NOT logic gates, translate the binary value to a decimal number which could then be displayed on a modified LED display through brute force (sort of like punch cards for each number, but wired in instead).
    I made a basic outline of the program, it can be done, I just don't really know all that much about computers. A clock would work, if I use one and know how to make delays I think I could get somewhere with this.
  • Paul BakerPaul Baker Posts: 6,351
    edited 2005-11-10 16:18
    Whew! ok Im glad I didnt have to explain how to design an async delay loop. What you want to do is use a hardware debounce circuit, which is nothing more than the switch, a resistor, a capacitor, and a schmitt trigger inverter. Here's a page that does a pretty good explanation of it: http://www.all-electric.com/schematic/debounce.htm

    PS, did you forget to attach the picture you are refering to?

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  • Paul BakerPaul Baker Posts: 6,351
    edited 2005-11-10 18:59
    You may still need some type of delay circuit, its hard to tell without a proposed schem, but the delay value doesn't need to be precise in this app, making the design simpler.

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  • Armored CarsArmored Cars Posts: 172
    edited 2005-11-11 14:31
    I think I can work with the stuff on that page for the amp thing, though I would still like to hear about making delays with a clock to use in my other projects.
  • Paul BakerPaul Baker Posts: 6,351
    edited 2005-11-11 17:37
    No prob, its pretty easy, it is simply a series of D type registers configured as a pipeline, where the output of one register is fed to the input of another. You set the resolution of the delay by the number of pipeline stages (IE if clock is 100 Hz and pipeline length is 10, the delay from input to output is .1 seconds), by dividing the clock you can increase the delay (at the cost of resolution, IE if clock is divided by 2 a pipeline depth of 5 is now equal to .1 second delay, but input is only sampled at 50Hz) , you can also make the delay dynamically adjustable by dividing the clock on the fly (again at the cost of resolution), or by having a multiplexor whose inputs are the output of various stages (100Hz clock, 10 stage pipeline, tieing an 8 to 1 multiplexor to the last 8 stages provides a 0.02 to 0.1 second delay in 0.01 increments). All this can be done in software as well by implementing a FIFO buffer. This is a very quick glossover, ask for clarification on any aspect you don't understand.

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