Your experience with CPLDs

Paul Baker

The discussion about the dicontinuance of the SX52 degenerated into a discussion of CPLDs. So I thought Id startup a new thread dedicated to its discussion. I'll start it by asking for stories from Parallax forum members about thier experience with CPLDs and what benifits/troubles you had with the particular company and the particular chip. I'll start with mine:

For last years SX design contest, my intended entry was a 50MHz digital storage scope (logic analyser), and it had a wealth of features, a 128KB buffer 15ns SRAM, 8 I/O channels with internal and external triggering, USB connection for uploading datasets, SD/MMC card interface for storing datasets, TV output to display datasets on television, 2 rotary encoders (spin and scroll) to navigate the dataset, SEEPROM to store user preferences, alphanumeric display to provide feedback (menus etc) when the unit was used out in the field, and numeric keypad entry.

Obviously, this requires way more I/O than a SX52 can provide, the obvious choice a CPLD or FPGA. I didnt like the external boot PROM of FPGAs so I decided to go with a CPLD. After comparing several different companies CPLD offerings, I decided on Atmel, they had alot of documentation and that made me think it was a safe choice. They also had a free program WinCUPL and directions on how to create an ISP JTAG programming cable.

Months later after I spent ~$150 on PCBs and components (not enough time left to do proper prototyping since I got into the contest late) I was at the step of writing the program for the CPLD. The documents for WinCUPL were volumous but vague, requiring me to constantly flip back and forth, reading and rereading passages. Wrote the state machine, didn't compile and spat out some gobbly-gook I couldn't find an explanation for in the·documents. Reduced the scope of the state machine, didn't compile, made the simplest circuit I could think of (rows of latches) it compiled. Ran the fitter software and it threw a fit (funny now, but not then), never could get the fitter software to work properly.

Missed the SX contest deadline, haven't worked on the board since, now Ive got a pretty and expensive paper weight.

In my height of frustration I wrote atmel seeking guidance. They responded that they didn't write the program, the company that did is out of business and they provide it as-is (ie no tech support), but if I wanted to purchase thier professional program ($199) they'd be happy to help (if I wasn't a polite person I would have told them where they could stick thier professional development package). Moral of the story is: good docs doesn't mean good customer service, and don't use atmel CPLDs.

What's your story?

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SteveW

That sounds like too good a project to let die, you know...
What Atmel part were you using?It's possible that the tortuous route of the Altera freebie tools targetting a 7000 device, run the output through Atmel's pof2jed tool, would let you escape from the hell that is wincupl, and finish development on your board.

Then again, the 30-day free trial of ProChip Designer V4.0 might also do the job. At first glance, it looks capable enough, and it should be orders of magnitude less annoying than wincupl, which, unless it's abandoned its roots, is a 15-year-old bit of software.

Of course, if a Xilinx CPLD happens to be pin compatible with your chosen CPLD, then the answer's pretty simple.

Steve

Rsadeika

Since I am not an EE, and to possibly provide a learning experience from these threads,·maybe a brief description of what a CPLD is, would be in order.

Paul Baker

CPLD stands for complex programable logic device, they are chips typically used as glue logic, though some are complicated enough to perform standalone processing, they are constructed from what are called macro-cells all which operate in parallel, so they can actually perform multiple operations at the same time, something which a standard processor cannot do. If you want more indepth explanation, do a google of CPLD, there are quite a few pages out there that go into as little or as much detail as you want.

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Paul Baker

Steve, the chip on my board is ATF1508AS-100TQFP which I think has 128 macrocells (not sure), I noticed there where equivalent packages availible from Xilinx, but I haven't investigated if they are pin compatible yet.

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Armored Cars

Can a CLPD be programmed by an SX key in Assembly? If I need another program will the SX Key still work or will I need a complete prototyping system? Also I have heard that CRLDs are weaker than the SX chips. Is this true and how so?

Paul Baker

It is theoretically possible for an SX to program a CPLD, but requires implementing the JTAG protocol on the SX (the SX would program the CPLD, not the SX-Key), but the JTAG protocol is difficult to get details on, Im a proficient searcher and I have yet to have found a comprehesive source of information on the subject.

CPLDs and microcontrollers are different beasts, they each have thier strengths and weaknesses. The strength of microcontrollers is thier ability to perform complex operations where one operation (instruction) is unique and indifferent to the other operations performed (in most circumstances you can program any instruction at any point), their weakness (for the vast majority, though there are exceptions) is they are serial in nature, they cannot perform multiple operations at the same time.

The strength of CPLDs is that they are parrallel in nature, CPLDs are comprised of macro-cells, and each operates independantly and simultaneously, so you can perform multiple operations at the same time, you can also define interrelationships between macro-cells so that you can increase the complexity of the operation performed. The weakness of CPLDs is that the operational ability of any single macro-cell is rather limited. Each macrocell at its heart is just a single bit register, feeding the input of the register is combinatorial logic which you define and which gets its input from external signals and other macrocells. CPLDs are a natural fit for state machines, and you can define many state machines within the CPLD at the same time, and they all work simultaneously, and can be independent of each other or interrelated, depending on how you program them.

So both CPLDs and microcontrollers have thier own place, and there are several new chips availible that actually combine both CPLD and a microcontroller onto the same chip so you can exploit the best of both worlds. Ive seen a chip that contains an programmable analog sub-block, a DSP and CPLD, and they can do amazing stuff such as real time MPEG encoding of a analog video signal.

I hope this clears up the difference between the two for you.

If you want more detail of how CPLDs are constructed look at the construction of a PAL (also called PLDs and GALs)·such as the 22V10, CPLDs are the same way but more complex (thats where the C in CPLD comes from).

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Post Edited (Paul Baker) : 11/2/2005 4:11:13 PM GMT

Armored Cars

I think I'll stick to the SX for now.

Ryan Clarke

Why the problem with an external boot prom? At least on our Altera boards we put that on board for you.

I haven't had a problem with that- Is it simply a matter of # of components?

Ryan

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Ryan Clarke
Parallax Tech Support

RClarke@Parallax.com

Paul Baker

My stated reason for not going with an FPGA was rather simplistic, first I have experience with PALs, CPLDs being an extension of PAL technologies makes more intuitive sense to my mind (I was trying to reduce the learning curve because of time restictions), second I needed a 100-TQFP package, can't go with Altera because all thier FPGAs in that package are sub 5 V and conversion logic for so many I/O pins was simply out of the question. All of Atmels 100-TQFP FPGAs are twice the price of CPLDs. Xilinx also didn't have a good fit for a 100-TQFP 5V FPGA.

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Kevin Wood

Altera has a a software eval CD that you can send for that includes Quartus II web edition, Nios II embedded processor, and a good set of tutorials. The challenge with CPLDs / FPGAs is that you have to know how to design the circuits. That being said, I think it would be cool if Parallax developed a curriculum similar to Stamps in Class around one of their development boards, perhaps the Cyclone FastPack, since it is the least expensive and is conceptually similar to a BoE. It would be a good next step above Stamps in Class, since you could approach the same ideas and concepts from a different perspective.