decoder or encoder?

Tbag

Forum members,·I am trying to get around using a microcontroller. Not because I don't like them (I have the BS2) but becuase inutitively I don't feel its necessary in this case. Since researching after·talking with a lot of you, and you were all very knowledgable, I feel I need to revisit.

I am driving a counter with a clock, and I want the clock's binary output to·a decoder to drive a gate. Problem is I need it to stay·in the "Hi" state (or lo) while the counter is on a particular number.·From what I have researched since my last post, the decoder output (as well as the counter) will·be a square wave oscillation of·Hi to Lo at a frequency less than the clock (f/2 to the n to be exact). I need an output that will stay Hi OR lo. The logic being that ultimately it will ultimately connect to a subcircuit that needs a steady state.

Could Mr.Lee Harker be correct in that we need to connect the counter to an ENCODER and not a decoder?

-Tbag

Paul Baker

You are correct that the function you want is a decoder, most of which are active low since most chip enables are active low.

The encoder does the reverse, outputing the binary of a input's position. Typically there is a priority for each line, in case more than one line is active at a time, frequently the name priority encoder is used.

<edit> I think I may have read your post wrong, let me study it a bit more. How many bits does your counter have? </edit>

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Post Edited (Paul Baker) : 8/23/2005 4:52:29 AM GMT

Paul Baker

I think you want a comparison operator, I think there is a seldom used 74 series chip that does it... Found a few, they are called identity comparators; there is the 520, 521, 524 and 688.

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Post Edited (Paul Baker) : 8/23/2005 5:06:19 AM GMT

KenM

Is there only one Counter Number where you want the output held Hi (or Low) during that number.....and what is the number?

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Ken

Paul Baker

That was the impression I got after re-reading his post, the identity comparator would permit him to compare the couter output against any arbitrary number, settable by dip switches or even a stamp.

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Tbag

Still, my question is, once a decoder pin is activated by a counter, is its output held steady until the counter changes or does it oscillate from hi to lo during that period?

Still confused,

Mr.T

Paul Baker

Decoders by there nature are asynchronous, meaning they do not have a clock signal, their output changes Tpd after the input changes. So the output's timing is determined by the input or your counter. Since counter outputs change only once per clock cycle, the decoder's output will change only once per clock cycle as well.

How many bits does your counter have, you understand that an encoder only has 3 inputs right? So if you have an 8 bit counter, you will need 32 decoders, plus additional circuitry to enable you to choose one arbitrary count value out of 256 possible count values, additionally if you choose to change the value you respond to you will need to physically disconnect it from the old line and connect it to the new line. The identity comparator circumvents all of this.

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Tbag

Ok, that's more clear to me, thanks. So lets say I connected an LED circuit to a decoder output binary 1. Everytime binary 1 is activated the LED stays lit. But if I connected an LED circuit to·output·1 of a counter without the decoder, the LED will flash until binary Q1 becomes zero. Is this correct?·I believe that the counter output is frequency related and the decoder a HI Lo?

-T.

Paul Baker

Ok, I think the best way to illustrate this is in the form of a table, lets assume the counter is·3 bits wide (I don't want to print out a 256 entry table, plus a decoder is 3 bits), the first column is the output of the counter, the second column is the Q^th decoder line which is activated (and yes a decoder has an active low output, meaning when it is active its voltage is 0, when it isn't, its voltage is Vdd), the third column is an LED whose cathode is connected to the counter's Q1 (the middle bit)·and anode is connected to ground via a current limiting resistor, the fourth column is an LED whose anode is connected to the decoder's Q1 and cathode is connected to Vdd via a current limiting resistor. The LEDs for each are connected differently because the output of the counter is active high, while the decoder's output is active low.

          LED  LED
cnt  dec  cnt  dec
 
000  Q0   off  off
001  Q1   off  on
010  Q2   on   off
011  Q3   on   off
100  Q4   off  off
101  Q5   off  off
110  Q6   on   off
111  Q7   on   off

 

Is this becoming clearer for you?

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Post Edited (Paul Baker) : 8/25/2005 11:08:20 PM GMT

Tbag

Ok, I think I see now. A binary counter is much like a group of bongo drummers who are always playing. Each peformer hits his drum at a steady interval and the one sitting to his right hits his drum at half speed of the man to his left. If you have 8 sitting in a line, drummer 2 is twice as fast as 3, four times as fast as 4, eight times as fast as 5, and so on. If they are syncronous, drum beats occuring singly or together with the cadence of the conductor (aka clock pulse negative edge). Sorry to use an anlogy but it helped me.

If we have a 10 digit binary counter connected to say a 1.2 Mhz clock source and we want an output frequency of 150 khz we would connect our circuit to the 3rd pin in the count. Therefor the resultant frequency is f/2^n or 1.2Mhz/2^5 = 150 khz.

The stimulus for this topic was driven by a need for a logic scenario to enable 3 seperate AND gate drivers sequentially at equal intervals and reset after the third to start again. Problem is that I beleive (underscore beleive) that attaching this to the first three outputs of a decoder with count four tied to reset would work BUT would render an asynchronous circuit becaise of the propagation time through the decoder which is not directly controlled by the counter clock. Therefor the answer is to create a shift register of D flip-flops and using a NOR gate tied in parallel to each D output to set the first bit to 1. You would connect in parralel the output of each D flip flop also to the enable of the AND gates and you get a sequential gate driver described above that is synchronous with the system clock.

I don't think there are any huge errors here but this has been a great debate over various design approaches to what was a seemingly simple problem. The prior thread from which this was started is a few threads down the forum under title "Is a stamp necessary in this case".

-T

Paul Baker

Your first two paragraphs are correct, the third requires a little more analysis, during lunch I'll look at it a bit more carefully.

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Paul Baker

Ok, the fact that you have 3 is problematic, if it were a power of two (like 4), it would be a simple solution. Ive never used one, but you may want to use a divide-by-N counter such as the CD4018 (I haven't read the specs to fully understand it's operation, so it may not work as expected). Alternatively you can get a counter (probably 4 bit) with a synchronous reset, then use an AND gate with Q0 and Q1 as input with the output feeding to the reset of the counter (or a NAND gate if the reset is an active low input), this should cause the counter to reset the counter the next cycle after state XX11, then you would hang a decoder off of Q0 and Q1 to drive the Q0-Q2 outputs of the decoder.

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Post Edited (Paul Baker) : 8/30/2005 5:14:23 PM GMT

Jim G.

I like your D flip-flop shift-register approach...

The 74(HC)175 is a quad D f/f that would work great.· As you mentioned, you would simply connect the output of one f/f to the input of the next one.

The proper sequence will be created by connecting a 2 input NOR gate to the first and second outputs, and the output of the NOR gate to the first D input.

One possible problem with this approach is that it·only cycles correctly after the first clock; when you power up the circuit ALL 3 outputs are low.· However, if you use a dual f/f chip with both reset and set pins, you can initialize the circuit to "100" and be OK...

Have fun...

Jim

Paul Baker

Ah yes there is always more than one way to skin a cat, the quad d ff will end up with less chip count, hence less space and less cost, go with that.

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Tbag

Thanks Paul!