SX28 Sound Card

cbmeeks

Ok, for those that don't know, I am building a homebrew computer.

My design is probably going to use a 6502 for the CPU and several SX28 (and maybe even some PICs) for the subsystems like audio, I/O, etc.

Anyway, I am working on my "sound card" now.

I would like my sound card to have it's own 32k of RAM and at least 4-8 bit resolution.

So....

If I use a parallel connection to the SRAM and use the 15 pins for the address bus, 2 pins for /OE and /WE that leaves me with only 3 pins. No where near enough for the 8 bit data bus PLUS the number of pins for my audio out.

What should I do? Should I try using a serial connection? Isn't that much more complicated and slower?

Should I ditch the SX28? I know some of the PIC "monsters" can get up to 40 pins (I have some) but I like the speed and power of the SX.
I don't think the SX52 would work unless I get the "con carne" version because I want DIP.

Thanks for any suggestions.

-cbmeeks

Bean

Parallax is going to have an SX52 proto board available soon (when Ken?). That very cheap ($10-$20).
Bean.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
"SX-Video·Module" Now available from Parallax for only $28.95

http://www.parallax.com/detail.asp?product_id=30012

Product web site: www.sxvm.com

"If you keep doing what you always did, you'll keep getting what you always got."
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cbmeeks

Darn...I just bought the $149 protoboard for the sx28 (and the wife doesn't know)..lol

I can't keep spending!!! :-/

cbmeeks

David B

You have a number of options.

I just posted a project where an SX28 uses a 512K CMOS RAM chip by sending port C to one of 4 places - a low-8 address latch, a middle-8 address latch, a high-3 address latch, or the RAM data bus. Port B operates a 74HCT139 data selector to trigger the appropriate latch and to operate the RAM control lines. It's working great.

If you're mainly going to use the RAM serially, you could use counters, like the 12 bit CMOS 4040 (if I remember correctly), to generate any number of address bits - the SX would only have to clock one line to increment all address lines.

David

cbmeeks

Thanks.

Any tips/tutorials on the 74HCT139?

I'm a newbie and only have a small understanding of latch registers.

thanks

cbmeeks

Bean

What I have been looking for is a SRAM chip that allows the address to be sent serially, has a increment pin to increment the address that was sent, and a parallal data bus. With a read speed of about 50nSec or so. I'm not worried about the write time.
Anyone know of one ? I know I can built it with multiple chips, but surely someone makes it.

It would be ideal for this project also.

Bean.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
"SX-Video·Module" Now available from Parallax for only $28.95

http://www.parallax.com/detail.asp?product_id=30012

Product web site: www.sxvm.com

"If you keep doing what you always did, you'll keep getting what you always got."
·

David B

All the 74HCT139 does is decode 2 lines into 4 states; its big brother 74HCT138 is the same except it decodes 3 to 8. For example, set the data bits to 0,1, and set the chip enable line, and the output bit "1" goes low.

They're pretty common on small computer systems; in fact, if you're building a small computer then this would be a prime candidate for selecting between your RAM and ROM.

In my project, I fed the SX port C to 3 74HCT573 8-bit latches, then when the appropriate 74HCT139 bit was selected, then released, those 8 bits are latched to the outputs of the HCT573's and thus to the RAM address lines.

cbmeeks

Cool. So it sounds like my SX28's can still be used?

So, for 32k, how many pins do you think will be needed for just the SRAM?

David B

I imagine you could get by with maybe 3 pins of control and 8 of data. Two control pins can address 4 selections which could latch the low 8 bits of address, latch the high 7 bits of address, send a WRITE command to RAM or send an OUTPUT ENABLE (READ) command to RAM. The third control line enables the selector to apply the address you've selected.

If you wanted, you could use control 4 pins: two to directly control latching of two address latches and two to directly operate the RAM controls, and forget that HCT139 decoder.

From my experience with wire-wrapping a couple of Z80 microcomputer boards, if you're planning to build a 6502 system I'm sure that you'll know this sort of design inside and out by the time you're done.

David

Paul Baker

Bean (Hitt Consulting) said...
What I have been looking for is a SRAM chip that allows the address to be sent serially, has a increment pin to increment the address that was sent, and a parallal data bus. With a read speed of about 50nSec or so. I'm not worried about the write time.
Anyone know of one ? I know I can built it with multiple chips, but surely someone makes it.

It would be ideal for this project also.

Bean.

The closest memory I can think of is VRAM, but that has a parallel and serial data access, I dont think the address is serial (though some variety of VRAM may support this).

My suggestion is to use a PLD front end to perform these functions, that is the route I decided to take when I needed too many pins on the SX52 for other purposes. The address lines are driven with a counter and latch and the default action when accessing the memory (reading and writing) is to post increment the address after access is complete (the latch is updated when the SX signals memory access is complete (by sending the function NULL). So random access of any memory address follows this command list: NULL-> LOAD_ADR (data on bus loaded into low address byte) -> NEXT1 (data on bus loaded into·middle address byte) -> NEXT2 (data on bus loaded into high address byte) -> READ_MEM (contents of memory on data bus) -> NULL (address is incremented), subsequent reads from sequential addresses is accomplished via READ_MEM, NULL combinations.

cbmeeks

Thanks guys!

Hey, I was looking at an old dead, NES mobo I have and guess what chip it has? A HD74LS373P. I think that is the latch IC I need.

Now, if I can only figure out how to de-solder it.

Heck, I might steal the CPU!!

cbmeeks