timming diagram SX52 and precise information about work @ > 100MHz
vls
Posts: 6
Please, anyone have the timming diagram of SX52? I need compare the oscilator timing and I/O port output. it´s because I use the same oscilator to other chips and I need synchronize it.
I need more information about work @ >100MHz also. It´s about the VCC and temperature. Please, I need precise information about it. I´m planning to work·@ 115MHz.
I´m developing a application (board and software) to video capture and output with USB 2.0 Hight Rate @ max. possible speed (the max possible speed to USB 2.0 is 480Mbps).
I´m on a paper yet. My Sx52 will arrive on next week. I need finalize the project in a month.
Thank´s
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I need more information about work @ >100MHz also. It´s about the VCC and temperature. Please, I need precise information about it. I´m planning to work·@ 115MHz.
I´m developing a application (board and software) to video capture and output with USB 2.0 Hight Rate @ max. possible speed (the max possible speed to USB 2.0 is 480Mbps).
I´m on a paper yet. My Sx52 will arrive on next week. I need finalize the project in a month.
Thank´s
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·· vls
Comments
As for the timing diagram I don't have it off hand but you could go look through the datasheet from Ubicom at http://www.ubicom.com/pdfs/SX-DDS-SX4852BD-15.pdf
Chris
thank´s
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That´s the datasheet i´m using...
I realy didn´t find anything about the relationship·of input clock and the I/O (timing).
thank´s
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I ´ve found a distributor of coolers to northbridge shipsets here in BRAZIL, it will be very important to this project. I did´nt decided if I will work at 100MHz·or 115MHz, maybe I will only know after practical tests.
I need to know the percentage of SX that passed to Parallax/Ubicom 100MHz tests for·my economic reasons and if Parallax/Ubicom can sell about 1.000 SX52 with pre test. Do you know how can I get this information?
Thank´s
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The power dissapated by a CMOS·integrated·circuit is Pcomp(mw) = (Cequiv(pf))*(Fave(MHz))*(V cc(volts) )2*(10-3), or the capacitance of the circuit times the speed of operation times the supply voltage squared. The current of a SX52 @ 75Mhz is nominally 106mA and a max of 150mA. This corresponds to a power of .5 Watts to .75 Watts, solving backwards for the equivalent capacitance of the circuit yeilds·.267 pF·to .4 pF. The maximum power dissapation of the SX52 is 1 Watt @ 70 C and 1.5 Watt @ 25 C. Solving forward for the expected power for 100MHz, we get·2/3 to 1 Watt. As you can see under the worst rating possible we have reached the maximum allowable power dissapation if the chip is operating at 70 C, and this is not accounting for any power consumed by pins configured as output. If you can keep the die temp near 25 C you'll have an additional budget of .5 Watts. The moral obviously is the cooler you can keep the chip the faster it will run. Since you can calculate the power consumption via the current draw of the chip, I would suggest drafting a prototype board, including the cooling fan and measure the current draw to calculate the power dissapation. If this is under a watt you should be fine. If you have alot of pins configured as output keep the current draw to a bare minimum, this means only driving high impedance/low capacitance·loads and reducing the trace length to a bare minimum (to reduce load capacitance) otherwise you are just increasing the total power the chip needs to consume and taking away from the chip's ability to operate at a higher speed . If you must drive a low impedance or high capacitance load, buffer the signal through an external logic circuit.
Like I said this should be possible if you properly design the active cooling system and reduce the current requirements of external connections.
You can ask Parallax if they have any documentation of the distribution of power consumption for SX52, but I don't know if they have such statistics. One thing you may be able to do, though you would have to work through this with Parallax is after you have done your prototype to ensure that it is theoretically possible to use an SX52 at that speed, to arrange an agreement with parallax to buy·rails of SX52's, design a testbed consisting of a ZIF socket for 52-PQFP, measure the current consumption of each chip @ 50Mhz and use calculations to determine what the power consumption of the chip would be at 100Mhz, then return chips which don't meet the criteria at a prearranged restocking fee. I dont know if they would be willing to do that and it is very important that you do not test them at full speed because they certainly wouldnt accept chips back that were run outside thier rated frequency.
Or you could after startup of production take your own statistical metrics and adjust the product cost according to anticipated failure rates.
Post Edited (Paul Baker) : 4/25/2005 6:18:35 PM GMT
I will think about it, I need to take a decision about work at this speeds.
Thank´s again.
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I think it is a very bad idea to suggest that Parallax should even consider such a thing.
The project is stated to require 1000 chips, then surely the budget could afford purchasing 10 for performance testing, and if those are 70% or more successful, then complete the design and purchase 100 for testing, and work the numbers up that way.
I for one would NOT be interested in purchasing from Parallax ANY product that had been powered up and returned by someone not on their payroll.
Peter (pjv)
I still have some of these devices. PM me if you're interested...
If I remember correctly the 100Mhz parts were so rated without the aid of active cooling so his yeild could be fairly good.
I thought of an additional idea though again its not very feasible or nessesarily advisable, that is replacing the plactic top of the case with a ceramic plate to aid in the thermal conductivity from the die to the heat sink, but I really think this is more hassle than it is worth and likely to produce a lower yeild of working components unless it is done in a clean room environment with the proper machinery and tools to do it.
I fear that if an operating speed of 115Mhz is absolutley nessesary then some other chip than te SX will need to be used.
Thank you, but i need a chip that is in line to produce in line.
Paul Baker:
I will make some tests, nothing better than burn some devices to knows·its limit. Anyway, i can not deal with change of·SX after mounted·(on the board,· in line production ), so it´s better now start with 75MHz and study a better device.
thank´s
Anyone·knows where to get de timing diagram of de SX52? In this project, i need to syncronize some devices in the board. I.E. How much time from the rising edge of oscilator and a change to a port I/O ?
thank´s again
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