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Logic levels — Parallax Forums

Logic levels

NewzedNewzed Posts: 2,503
edited 2005-03-14 20:42 in BASIC Stamp
What are the logic levels for a Stamp - 1.7 for a LOW and 3.4 for a HIGH?

If the pin is at 1.8-3.3, would the indicated state be the last state it was in?

Sid

Comments

  • Chris SavageChris Savage Parallax Engineering Posts: 14,406
    edited 2005-03-14 18:01
    Sid,

    ·· The threshold for a logic level 0 is 1.4V on the stamp.· Anything below 1.4V·is low (0), and anything·above ·1.4V·that should be high (1).




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    Chris Savage

    Parallax Tech Support
    csavage@parallax.com

    Post Edited (Chris Savage (Parallax)) : 3/14/2005 6:13:47 PM GMT
  • Beau SchwabeBeau Schwabe Posts: 6,568
    edited 2005-03-14 18:34
    Sid,

    What you are describing is a schmitt trigger input which has a hysteresis region in the middle.

    The Stamp has a TTL level that trigger at 1.4V

    Stamp Manual

    See pages 138,327, and 352

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    Beau Schwabe - Mask Designer III

    National Semiconductor Corporation
    (Communication Interface Division)
    500 Pinnacle Court, Suite 525
    Mail Stop GA1
    Norcross,GA 30071
  • Chris SavageChris Savage Parallax Engineering Posts: 14,406
    edited 2005-03-14 20:42
    TTL chips (Like the 74xx series), especially older logic chips do have that middle region.· But the stamp has a solid 1.4V point with .1V crossover to prevent an intermediate signal.· It's TTL compatible.




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    Chris Savage

    Parallax Tech Support
    csavage@parallax.com
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