Speed of Edge Detection on PORT B

Analog1

Hello every one!

Can I detect a 10 nano second pulse on PORTB with the edge detection feature turned on.

Thanks in advance,

Analog1

allanlane5

Isn't this in the SX PDF manual?

OK, a quick perusal shows no, it isn't.· So, how short a pulse CAN portB detect?

Post Edited (allanlane5) : 3/8/2005 2:57:07 PM GMT

Guenther Daubach

Consider an SX clocked at 50 MHz. This means the clock period is 20 ns, i.e. twice as long as the pulse you want to catch.

Nevertheless, IMO, the minimum possible pulse length for PORTB's edge detection is not directly related to the controller's clock speed but it can become an issue if the pulses come in faster than the SX can handle them due to the clock frequency of 50 MHz "only" .

Well, this does not answer your question as well, and I could not find any information in the docs eiter. I think the only way to find that out is running tests with a real SX.

Analog1, or anyone else, do you have a pulse source available that can generate such short pulses? Would be interesting to learn about the results.

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G

Paul Baker

whats the min input pulse width of a 555 astable monovibrator configuration? Is it defined by the current of the pulse into it, if so you can use a high speed op amp to source it if your pulse generator can't source the required current packet trigger.

Bean

Yeah, that's a good idea. The ol' pulse strecher circuit.
Bean.

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pjv

Hi All;

As this issue is also interesting to me, I decided to do some tests, and here are the results.

Operating at 5 volts and room temperature, turbo mode, and triggering·the pulse into·port B.0, the threshold of pulse detection was 5 nano seconds (as·short as my pulse generator will go) with about 80% success. Stretching this to 6 nano seconds or longer brought the detection to 100%.

It worked identically for detecting rising and falling edges, and it captured equally well at 50 Mhz using SX-Key's clock·and 4Mhz internal clock.

At 50 Mhz the minimum delay time in entering interrupt was 100 nano seconds, equal to 5 instructions, and the maximum delay was 120 nano seconds, the difference of course being the asynchronicity between the pulse generator and the processor clock.

At 4 Mhz the minimum delay time in entering interrupt was 1000 nano seconds, equal to·4 instructions, and the maximum delay was 1250 nano seconds.

It would appear that·there is some 20 nano seconds of transit delay which of course is not noticable at the slower speed, but shows up as the equivalent time of one instruction at 50 Mhz.

The delay testing was done by triggering one channel of my oscilloscope on the pulse edge, and observing an RB.7·bit-set flag as the first instruction in the interrupt on another channel. The scope bandwidth was set to 500 Mhz.

Because the observable bit-set (read-modify-write) occurs near the end on a processor cycle, the·duration of the bit-set instruction (20 nano seconds for the 50 Mhz case) was subtracted from the observed time, giving the net results indicated above. In other words, the actual time observed on the scope was one instruction longer time than the true time to enter interrupt; the final instruction cycle does not count in determining the number of cycles to get from the pulse edge into interrupt.

Hope this helps, have fun experimenting,

Peter (pjv)
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James Newton

Was that an SX 28? May we know the revision? May I publish that result at sxlist.com?

http://www.sxlist.com/intpulse

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pjv

Hi James;

How silly of me not to mention that; yes it was on a '28. The revision I'm not sure offhand.
Furthermore, the level settings were CMOS, pullups on, Schmidt trigger off.

Also·I used RC.7 (instead of my posted RB.7) as my scope indicator flag, but that should have had no impact.

Sure, please put it on your site.

Peter (pjv)

Post Edited (pjv) : 3/9/2005 2:04:16 AM GMT

Analog1

Peter,

Thank you for the prompt and thorough analysis. It is greatly appreciated.

Analog 1