Interface Java Stamp with CPLD
mza3000
Posts: 6
Hi,
I'm working on a project to interface a Java stamp with a CPLD. Essentially, I'm trying to create a bi-directional interface between the 2 chips. For example, I'd like to be able to send an 8 bit value from the Java stamp's digital outputs·to the CPLD's digital inputs, and·send an 8 bit value from the CPLD's digital outputs to the Java stamp's digital inputs. The two chips will be hard-wired together, and the CPLD will be programmed in VHDL. My intent is to send the data serially. I just assume send the data serially rather than in parallel·to reduce the number of·external wires in·my system (and also I/O ports will eventually be a limiting factor in my design).
Can anyone·give me a high level discription of what needs to take place (or be constructed) on the Java stamp side (possibly Java code/psudo-code)·and on the CPLD side (possibly VHDL code/psudo-code)?
I'm in the preliminary design stage, and at this point all I really know is that I'll need to attach a START_BIT and a STOP_BIT to the data, and send this·8+2=10bit string·at an agreed upon rate (ie: 2.4kbps), and on the CPLD side have a shift register shifting in the data 1 bit at a time until the STOP_BIT is detected. So essentially the CPLD will be in an idle state until it detects data on it's digital inputs (coming from the Java stamp's digital outputs).
Any help/suggestions/code would be most appreciated.
Thanks,
mza3000
I'm working on a project to interface a Java stamp with a CPLD. Essentially, I'm trying to create a bi-directional interface between the 2 chips. For example, I'd like to be able to send an 8 bit value from the Java stamp's digital outputs·to the CPLD's digital inputs, and·send an 8 bit value from the CPLD's digital outputs to the Java stamp's digital inputs. The two chips will be hard-wired together, and the CPLD will be programmed in VHDL. My intent is to send the data serially. I just assume send the data serially rather than in parallel·to reduce the number of·external wires in·my system (and also I/O ports will eventually be a limiting factor in my design).
Can anyone·give me a high level discription of what needs to take place (or be constructed) on the Java stamp side (possibly Java code/psudo-code)·and on the CPLD side (possibly VHDL code/psudo-code)?
I'm in the preliminary design stage, and at this point all I really know is that I'll need to attach a START_BIT and a STOP_BIT to the data, and send this·8+2=10bit string·at an agreed upon rate (ie: 2.4kbps), and on the CPLD side have a shift register shifting in the data 1 bit at a time until the STOP_BIT is detected. So essentially the CPLD will be in an idle state until it detects data on it's digital inputs (coming from the Java stamp's digital outputs).
Any help/suggestions/code would be most appreciated.
Thanks,
mza3000
Comments
2. If you don't do #1 above, then it sounds like you are trying to implement a UART in the CPLD. Most UART's sample the signal at three times the baud rate, in order to find the mid-bit region. Once a start-bit is seen, then the NEXT clock signal is used as the mid-bit sample clock. I think it is a more efficient use of your CPLD gates to implement the SPI interface.